Hi Per, > >Following the "trust but verify" principle, I was perusing the SV standard >to check your assertion that functions are a superset of non-time >consuming tasks. To my suprise I discovered that the syntax for >functions allow wait statements. In Section 12.3, p. 155 of P1800 it >is shown that a function definition can have zero or more >function_statement_or_null in its body. If you read further in >appendix A it turns out that function_statement_or_null can be >a function_statement and a function_statement is just a statement >which includes wait, see Section A.6.3, p. 532. Does this mean that >functions can be time consuming as well? Unless I overlooked something >it looks like the syntax allows it. [Shabtay] I further investigated it with some of our SV working group members and it seems that you indeed uncovered a bug (or at least ambiguity) in the spec. He promises to find out more and have this corrected. However, section 26.1.1 third paragraph clearly states that "All functions used in DPI are assumed to complete their execution instantly and consume zero simulation time, just as normal SystemVerilog functions." We thus believe that this strong statement reflects the intent of the SV standard and that your discovery will be fixed to match this statement. Regards, ShabtayReceived on Tue Oct 10 08:57:22 2006
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