RE: Some review feedback on the DPI chapter

Hi All,

I assume that there is some errata document going around the SV working
group.  I say this because it appears that ModelSim and IUS seem to be
in sync wrt. SystemVerilog functions.  

Maybe someone can find out if this is true and distribute the errata
document to the ITC group?

Thanks,
Jason

> -----Original Message-----
> From: owner-itc@eda.org [mailto:owner-itc@eda.org] On Behalf Of Per
Bojsen
> Sent: Tuesday, October 10, 2006 10:11 AM
> To: John Stickley
> Cc: Shabtay Matalon; itc@eda.org
> Subject: Re: Some review feedback on the DPI chapter
> 
> > It kind of shows that if you just blindly follow BNF grammar to see
> > what syntax allows, that does not necessarily match with what
> > intended semantics allow.
> 
> Well, yes, this is common, though.  Usually, the grammar is simplified
> and does not encode all the semantic restrictions.  For instance, it
> is usually not encoded in the grammar that a variable must be declared
> before it is used in languages where this is true.  But in this case,
> I found it especially interesting that the grammar allows wait
statements
> in function bodies.  This is different from the above.  If wait
> statements are not allowed, they should not be in the grammar.  It is
> not a matter of adding clarifying text.  The grammar should be fixed
in
> this case.
> 
> Is there a use of a 0-time wait here that I am overlooking though?
> 
> I have to admit I was quite surprised to see the grammar equal
> tasks and functions with respect to the statements allowed.
> 
> Per
>