What's in a function ?

Greetings ITC Techies,

I've received some information from some of our internal
experts regarding what is and isn't allowed inside
functions.

To understand the whole picture you really have to
read two LRMs. And, in the words of our expert, "sometimes
even then you're left scratching your head" ! :-(

However, in general, IEEE 1364-2005 still governs
the detailed aspects of Verilog that still apply
in SystemVerilog and P1800 governs specifically the
added features of SystemVerilog.

It is still the case that P1800 is lacking in
some of the more subtle details of the Verilog subset
of the language and you need both LRMs to cover
the whole language in detail.

And, according to him, 1364-2005 still forbids non-blocking
assignments, event triggers, and certainly anything that
would cause the calling process to block - including
wait statements.

So this apparently is why ModelSim rightly forbids
non-blocking assignments in functions.

For this reason, I think it behooves us to add
at least 0-time exported DPI tasks to the SCE-MI
2 subset so that we can allow at least scheduling
of non-blocking assignments. Bear in mind that
doing so does not cause any blocking of the calling
process. Merely a 0-time interaction with the scheduler.

Whether we go th extra step of allowing time advance I think
still remains a matter of debate. As I said earlier,
I certainly see its usefulness from a user point
of view.

-- johnS

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John Stickley                   \             \     \
Mgr., Acceleration Methodologies \             \________________
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