Undesired interface feature for latest pipes?

From: Jason Rothfuss <rothfuss_at_.....>
Date: Mon Oct 16 2006 - 14:54:52 PDT
Hi John,

 

I was digging into pipes some more and noticed that the original Pipes
proposal stated that the Pipe ID was a "unique intra-module pipe
identifier", meaning that the pipe could only be used within a single
scope (cannot be shared).

 

The recent version of Pipes using interfaces does not have the
restriction of only calling the pipe from the parent scope.  In a
SystemVerilog compliant simulator, I can instantiate a pipe in a parent
module and pass the interface to its children as well as its
grandchildren, and so on.  Was this intended?  I can imagine that this
can make the pipes implementation more complex (but not impossible).

 

Attached is a small example that should work in any SystemVerilog
simulator to illustrate the pipe instance 'top.pipe0' is shared among
scopes: 'top', 'top.c1', 'top.c2', 'top.c1.c1', 'top.c2.c1'.  You can
compile scemi_pipe.sv and example.sv and elaborate 'top'.

 

Please let me know if this is the desired behavior for pipes, otherwise
we should discuss how to get the desired behavior at our next meeting.

 

See below for simulator output of this test case:

 

 

                   0 top.c1 sending 1

                   0 send called (top.pipe0.send.send_body)

                   0
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[0] = 1

                   0 send buffer addr 0

 

                   0 top.c1.c1 sending 100

                   0 send called (top.pipe0.send.send_body)

                   0
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[1] = 100

                   0 send buffer addr 1

 

                   0 top.c2 sending 1

                   0 send called (top.pipe0.send.send_body)

                   0
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[2] = 1

                   0 send buffer addr 2

 

                   0 top.c2.c1 sending 100

                   0 send called (top.pipe0.send.send_body)

                   0
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[3] = 100

                   0 send buffer addr 3

 

                   5 top.c1 sending 2

                   5 send called (top.pipe0.send.send_body)

                   5
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[4] = 2

                   5 send buffer addr 4

 

                   5 top.c1.c1 sending 99

                   5 send called (top.pipe0.send.send_body)

                   5
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[5] = 99

                   5 send buffer addr 5

 

                   5 top.c2 sending 2

                   5 send called (top.pipe0.send.send_body)

                   5
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[6] = 2

                   5 send buffer addr 6

 

                   5 top.c2.c1 sending 99

                   5 send called (top.pipe0.send.send_body)

                   5
top.pipe0.send.send_body.unmblk1.send_for_loop.buffer[7] = 99

                   5 send buffer addr 7

 

 

Regards,

Jason

 

Jason Rothfuss 
Verification Acceleration R&D 


Cadence Design Systems, Inc.
54 Columbia
Irvine, CA 92612 

Office:

 

+1 (408) 944-7180

Mobile:

 

+1 (310) 210-2754



rothfuss@cadence.com
www.cadence.com 

 

  <http://www.cadence.com> 

 




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Received on Mon Oct 16 14:55:09 2006

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