Re: my action item for explaining semantics of notify callbacks in SCE-MI pipes

Shabtay,

Shabtay Matalon wrote:
> Hi John,
> 
>  
> 
>  From your response I deduct that the criteria set for a callback to be 
> called is that “a number of elements (1 to n) were moved by the call at 
> the control of caller”. 
> One this criteria has been established, the 
> callback will actually be called _only once_ when the caller yields 
> control to the other end.

johnS:
Yes, but you should probably say "before the caller yields".

> 
>  
> 
> Please confirm that under all circumstances you are proposing that the 
> callback will be called only once.

johnS:
"Under all circumstances" ?  No, only under the circumstance
that the pipe state (i.e. #elements in the pipe) changes during
a contiguous interval of execution within the caller thread.

> 
>  
> 
> Note: I believe that you provided 2 conflicting responses for the case 
> that two try_send do move data w/o a yield in between.  Is it one or two 
> callback invocations once the caller yields?

johnS:
In my example because the 1st try_send moved some but not all the
requested elements, a yield was necessary in between. There were
two callbacks because each try_send() resulted in adding elements.

So, the sequence is:

scemi_pipe_hdl_send(){

    ...

    try_send(); # 1st call - moves some but not all requested elements

    ...

    (*callback)();

    ...

    yield();  # Yield since we can't return until all elements moved.

    ...

    try_send(); # 2nd  call - succeeds in moving remaining requested elements

    ...

    (*callback)()

    ...

    return;
}


> 
>  
> 
>  
> 
>  
> 
>>  Now, the condition for the HDL side to yield control to the SW side is
> 
>>  only based on HDL side blocking call being blocked, an explicit flush
> 
>>  call issued by the HDL producer and an OEM sent into the channel in
> 
>>  autoflush mode.
> 
>  
> 
> johnS:
> 
> Correct.
> 
>  
> 
> [Shabtay] Your reply clarified the HDL side to SW side yield condition.

johnS:
Well yes. In other words if a blocking call is made from the
HDL side a yield must occur somewhere if the call cannot be
satisfied before returning due to a full (in case
of output pipe) or empty (in case of input pipe) pipe right ?

-- johnS
<eom>


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