This guideline, while good to follow, is probably the one that Cliff gets the most argument about. It has to do with still using blocking assigns within sequential clocked blocks to model intermediary combinatorial values. My understanding from Cliff is that he recommends avoiding this because if such values are read by a different clocked block, you can get a sim/synth mismatch. But if you're careful to avoid this however, it is possible, in some circumstances to avoid creation of the extra combo block and use results returned from functions for "downstream" logic wi -----Original Message----- From: owner-itc@server.eda.org on behalf of Bernard Deadman Sent: Thu 6/28/2007 2:53 PM To: Per Bojsen Cc: 'itc@eda.org' Subject: Re: more on Bernard's SCE-MI 2.0 issue Hi Per, I try to adopt the rules in: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf where you'll find: Guideline #5: Do not mix blocking and nonblocking assignments in the same always block. Clearly a blocking assignment to a variable breaks this guideline, plus there's another example of a redundant assignment in the same clocked block: dummy_rv = ReportTransaction( TransactionArg_q_r ); The 'dummy_rv' variable is never used so hopefully it gets optimized away. As I said before, I'm no synthesis guru! Regards Bernard Per Bojsen wrote: >> >> c <= SetResponse( argument )[ `my_slice ] > Actually I tried this but the problem I got into is Verilog won't > allow me to slice the return value of a function call, for example I > can't do: > > I hadn't thought of this. In that case the local variable is > necessary. But I still think synthesis should be able to handle > it. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jun 28 12:15:13 2007
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