//===========================================================================
// ClockAdvancer                                                johns 9-13-00
//
// The ClockAdvancer module counts DUT clocks until the requested
// number of cycles has transpired, then sends back a reply transaction.
//
// JAR: Jason Rothfuss
//===========================================================================

module ClockAdvancer(
      //inputs                              outputs
      //--------------------------          ----------------------------
        Uclock );

        parameter ClockNum = 1;
        parameter SampleWidth = 32;
        input Uclock;
            // Note: This is not necessary since uclock is available
            // from the internal clock macro.  However, it is placed
            // to prevent synthesis tools from unscrupulously optimizing
            // the entire module out since it has no I/O's (since
            // connections come from internal SCE-MI macros and there
            // are no external DUT connections).
//  {
    // Internal signals
    wire [31:0] advanceDelta;
    reg  [31:0] cycleCount;

    wire inReceiveReady;
    reg outTransmitReady;
    reg readyForCclock;
    wire [SampleWidth-1:0] inMessage, outMessage;

    assign inReceiveReady = 1;
    assign advanceDelta = inMessage[31:0];
    assign outMessage = 0;

    SceMiClockControl #(ClockNum) sceMiClockControl(
      //Inputs                              Outputs
      //----------------------------        ----------------------------
                                            .Uclock(uclock), .Ureset(ureset),
        .ReadyForCclock(readyForCclock),    .CclockEnabled(cclockEnabled),
        .ReadyForCclockNegEdge(1'b1),       .CclockNegEdgeEnabled() );
 
    SceMiMessageInPort #32 sceMiMessageInPort(
      //Inputs                              Outputs
      //----------------------------        ----------------------------
        .ReceiveReady(inReceiveReady),      .TransmitReady(inTransmitReady),
                                            .Message(inMessage) );
 
    SceMiMessageOutPort #32 sceMiMessageOutPort(
      //Inputs                              Outputs
      //----------------------------        ----------------------------
        .TransmitReady(outTransmitReady),   .ReceiveReady(outReceiveReady),
        .Message(outMessage) );

    always @(posedge uclock) begin // {
        if (ureset) begin
            outTransmitReady <= 0;
            cycleCount <= 0;
            readyForCclock <= 0;
        end

        else begin // {
            // Start operation command
            if( inTransmitReady &&
                    !outTransmitReady ) begin
                cycleCount <= advanceDelta;
                readyForCclock <= 1;
            end

            //----------------------------------------------------------
            // Set outTransmitReady to '0' by default, and then override
            // if we have data ready.  Otherwise, deadlock would occur
            // because if outReceiveReady was '1', outTransmitReady will
            // always be '0'.
            //
            // JAR
            //----------------------------------------------------------
            if (outReceiveReady == 1)
                outTransmitReady <= 0;
            if( readyForCclock && cclockEnabled ) begin
                if (cycleCount == 1)  begin
                    outTransmitReady <= 1;
                    readyForCclock <= 0;
                end
                cycleCount <= cycleCount - 1;
            end

        end // }
    end // }
endmodule // }