//=========================================================================== // Destination.v johns 10-2-00 // // The Destination transactor accepts tokens arriving from a point-of-exit // on the RouteMap and passes them to the SceMiMessageOutPort. // // Because we don't want to lose potentialy successive tokens arriving // from the RouteMap to this destination portal, we deassert // readyForCclock in the event that a token comes in but the // message output port is not able to take it because of tokens // simultaneously arriving at other destination portals. This way, we // guarantee that the entire RouteMap is disabled until all tokens are // offloaded from the requesting destination transactors. // // JAR: Jason Rothfuss //=========================================================================== module Destination ( //inputs outputs //-------------------------- ---------------------------- // DUT port interface TokenIn ); input [31:0] TokenIn; // { wire [3:0] destID; reg readyForCclock; reg outTransmitReady; reg [31:0] outMessage; wire oTr; wire [31:0] oMsg; reg [31:0] TokenIn_z1; // JAR: register the token so that we prevent // JAR: multiply sending tokens to the output // JAR: port. assign destID = TokenIn[7:4]; initial TokenIn_z1 = 32'b0; SceMiClockControl sceMiClockControl( //Inputs Outputs //---------------------------- ---------------------------- .Uclock(uclock), .Ureset(ureset), .ReadyForCclock(readyForCclock), .CclockEnabled(cclockEnabled), .ReadyForCclockNegEdge(1'b1), .CclockNegEdgeEnabled() ); SceMiMessageOutPort #32 sceMiMessageOutPort( //Inputs Outputs //---------------------------- ---------------------------- .TransmitReady(outTransmitReady), .ReceiveReady(outReceiveReady), .Message(outMessage) ); //------------------------------------------------------------------- // Re-write of the main always block. // outTransmitReady would remain asserted even if the OutPort // had accepted the data, thus repeatedly transmitting the same // data to the SW side. // // JAR //------------------------------------------------------------------- assign oMsg = (TokenIn_z1 != TokenIn & |TokenIn[7:4]) ? TokenIn : 32'b0; assign oTr = |oMsg[7:4] ? 1'b1 : 1'b0; always @(posedge uclock) begin:JAR if (ureset) begin outMessage <= 32'b0; TokenIn_z1 <= 32'b0; outTransmitReady <= 1'b0; end else begin TokenIn_z1 <= TokenIn; //---------------------------------------------------------------- // Wait for the token value to change. This is our indication // that valid data has arrived. // // JAR //---------------------------------------------------------------- if ((TokenIn_z1 != TokenIn) & |TokenIn[7:4]) begin outMessage <= TokenIn; outTransmitReady <= 1'b1; end else if (outReceiveReady & outTransmitReady ) begin // Token has been accepted outMessage <= 32'b0; outTransmitReady <= 1'b0; end end end // block: JAR always@( posedge uclock ) begin // { if( ureset == 1 ) begin readyForCclock <= 1; //outMessage <= 0; //outTransmitReady <= 0; end else begin // { // if( DUT clock has been disabled ) // It means that this destination transactor is waiting to // unload its pending token and does not want to re-enable the // DUT until that token has been offloaded or else it may // loose arriving tokens in subsequent DUT clocks. if( readyForCclock == 0 ) begin // When the SceMiMessageOutPort finally signals acceptance // of the token, we can re-enable the DUT clock. if( outReceiveReady ) begin readyForCclock <= 1; //outTransmitReady <= 0; end end else if( cclockEnabled && destID != 0) begin //outMessage <= TokenIn; //outTransmitReady <= 1; // if( token arrives but portal is not ready ) // Stop the assembly line ! (a.k.a. disable the DUT) if( outReceiveReady == 0 ) readyForCclock <= 0; end end // } end // } endmodule // }