module ClockAdvancer(
      //inputs                              outputs
      //--------------------------          ----------------------------
        Uclock );

        parameter ClockNum = 1;
        parameter SampleWidth = 32;
//  {
    // Internal signals
    wire [31:0] advanceDelta;
    reg  [31:0] cycleCount;

    wire inReceiveReady;
    reg outTransmitReady;
    reg readyForCclock;
    wire [SampleWidth-1:0] inMessage, outMessage;

    assign inReceiveReady = 1;
    assign advanceDelta = inMessage[31:0];
    assign outMessage = 0;

    SceMiClockControl #(ClockNum) sceMiClockControl(
      //Inputs                              Outputs
      //----------------------------        ----------------------------
                                            .Uclock(uclock), .Ureset(ureset),
        .ReadyForCclock(readyForCclock),    .CclockEnabled(cclockEnabled),
        .ReadyForCclockNegEdge(1'b1),       .CclockNegEdgeEnabled() );
 
    SceMiMessageInPort #(SampleWidth)32 sceMiMessageInPort(
      //Inputs                              Outputs
      //----------------------------        ----------------------------
        .ReceiveReady(inReceiveReady),      .TransmitReady(inTransmitReady),
                                            .Message(inMessage) );
 
    SceMiMessageOutPort #32 sceMiMessageOutPort(
      //Inputs                              Outputs
      //----------------------------        ----------------------------
        .TransmitReady(outTransmitReady),   .ReceiveReady(outReceiveReady),
        .Message(outMessage) );

    always @(posedge uclock) begin // {
        if (ureset) begin
            outTransmitReady <= 0;
            cycleCount <= 0;
            readyForCclock <= 0;
        end

        else begin // {
            // Start operation command
            if( inTransmitReady &&
                    !outTransmitReady ) begin
                cycleCount <= advanceDelta;
                readyForCclock <= 1;
            end

            if( readyForCclock && cclockEnabled ) begin
                if (cycleCount == 1)  begin
                    outTransmitReady <= 1;
                    readyForCclock <= 0;
                end
                cycleCount <= cycleCount - 1;
            end

            if (outReceiveReady == 1 && outTransmitReady == 1)
                outTransmitReady <= 0;
        end // }
    end // }
endmodule // }