module Destination ( //inputs outputs //-------------------------- ---------------------------- // DUT port interface TokenIn ); input [31:0] TokenIn; // { wire [3:0] destID; reg readyForCclock; reg outTransmitReady; reg [31:0] outMessage; assign destID = TokenIn[7:4]; SceMiClockControl sceMiClockControl( //Inputs Outputs //---------------------------- ---------------------------- .Uclock(uclock), .Ureset(ureset), .ReadyForCclock(readyForCclock), .CclockEnabled(cclockEnabled), .ReadyForCclockNegEdge(1'b1), .CclockNegEdgeEnabled() ); SceMiMessageOutPort #32 sceMiMessageOutPort( //Inputs Outputs //---------------------------- ---------------------------- .TransmitReady(outTransmitReady), .ReceiveReady(outReceiveReady), .Message(outMessage) ); always@( posedge uclock ) begin // { if( ureset == 1 ) begin readyForCclock <= 1; outMessage <= 0; outTransmitReady <= 0; end else begin // { // if( DUT clock has been disabled ) // It means that this destination transactor is waiting to // unload its pending token and does not want to re-enable the // DUT until that token has been offloaded or else it may // loose arriving tokens in subsequent DUT clocks. if( readyForCclock == 0 ) begin // When the SceMiMessageOutPort finally signals acceptance // of the token, we can re-enable the DUT clock. if( outReceiveReady ) begin readyForCclock <= 1; outTransmitReady <= 0; end end else if( cclockEnabled && destID != 0 ) begin outMessage <= TokenIn; outTransmitReady <= 1; // if( token arrives but portal is not ready ) // Stop the assembly line ! (a.k.a. disable the DUT) if( outReceiveReady == 0 ) readyForCclock <= 0; end else if( outTransmitReady == 1 && outReceiveReady == 1 ) outTransmitReady <= 0; end // } end // } endmodule // }