3) I propose to add the [following] NOTE at the bottom of p. 31. 

NOTE--The 1/1 cclock in Figure 13 has a frequency that is 1/2 
the frequency of uclock. This is a consequence of the duty 
cycle and phase requirements of cclocks cclock2 through cclock5 
and the SCE-MI requirement that both edges of a cclock with 
a non-don't care duty cycle must coincide with some rising 
edge of uclock. 

[Duaine countered with:] 

Making the suggested point at that location in the specification 
takes away from the topic at that location which is multiclock 
alignment. If there needs to be an example, it should be at the 
point where uclock and clock relationships are being discussed. 

[I am willing to take this one off the table and/or defer it to 
an app note on sane clock control or similar tutorial.]