From: Adam.Pawlak@imag.fr (Adam Pawlak ) Subject: Workshop-on-Component-Libraries:CALL-for-Papers To: randyh@Synopsys.COM (Randolph E. "Randy") Date: Wed, 26 Oct 1994 18:37:49 +0100 (MET) X-Mailer: ELM [version 2.4 PL13] X-UIDL: 783219873.009 Subject: CALL FOR PAPERS: IFIP WORKSHOP on LIBRARIES OF MODELS ============================================================== Dear Mr. Harr, May I bring to your attention an Event which I believe can be of interest to you and/or your colleagues. The Workshop on: LIBRARIES, COMPONENT MODELING, MODEL VERIFICATION AND QUALITY ASSURANCE following VHDL-FORUM Spring Working Conference will take place on 26-27.04.1995 in Atlanpole - La Chantrerie, Nantes, France. This Workshop is organized by the ESPRIT ESIP Project in cooperation with IFIP W.G. 10.5 and ECSI - European CAD Standardization Initiative. It will concentrate on the theme "Libraries of models". Please consult the "CALL for Papers" enclosed for the list of topics being covered. Three kinds of contributions are solicited: regular papers, experience reports and demonstrations. Best papers will be considered for publication in the special issue of Kluwer series "Current Issues in Electronic Modeling". Will you please consider an active participation in this event. Kind regards, Adam Pawlak Workshop Chair ___________________________________________________________________________ ESPRIT Project 8370 - ESIP C A L L F O R P A P E R S Workshop on Libraries, Component Modelling, Model Verification and Quality Assurance In cooperation with: IFIP W.G. 10.5 ECSI Following VHDL-FORUM Spring Working Conference 26-27.04.1995 Atlanpole - La Chantrerie, Nantes, France ____________________________________________________________________________ System designers need libraries of component models. Current libraries of models are in most cases neither portable nor compatible. This is caused by the lack of generally accepted rules for the development of models. The VITAL initiative is a big step forward changing this scenario for ASIC models. High model development costs for complex components and difficulty to protect proprietary rights of model developers constitute further obstacles. The objective of this workshop is to gather engineers developing models and responsible for libraries of components, designers using models in a board-level simulation, vendors developing tools, and academic people to discuss the state-of-the-art problems and solutions related to building libraries of sign-off, accurate, fast, portable, compatible and correct models of digital, analogue and mixed components. Papers are solicited on methods and tools in all areas related to the development of library models. Models in VHDL are of main concern but contributions presenting the experience accumulated in libraries written in other languages, and translation between different libraries are also relevant to the workshop. The program of the workshop will comprise: regular paper sessions, short presentations in the form of experience reports, demonstrations of software, and panels. Panels accompanied by tutorials will present latest results of standardization bodies in IEEE DASC, EIA and IEC. This workshop will also present results of the ESPRIT project 8370 ESIP - EDA Standards Integration and Promotion. INFORMATION FOR AUTHORS All submissions (written in English) will be refereed. Regular papers presenting an original work should not exceed 20 pages (12 point font, 1.5 spacing) including title page and max 100 words abstract. Experience reports should not exceed 10 pages presenting results of experiments clearly stating software and hardware environment of the work being presented. Experience reports on application of standards relevant for libraries are especially welcome. Submissions for software demonstrations should present software, its purpose and platform, and describe the intended demonstration. Proceedings will be available at the Workshop. Selected papers will be candidates for publication in a special issue of "Current Issues In Electronic Modeling", a series published by Kluwer Academic Publishers and edited by Jean-Michel Berge, Oz Levia, and Jacques Rouillard. SUBMISSIONS 5 copies of a regular paper or an experience report should be submitted by 16.01.1995 to the Program Chair. Notifications of acceptance will be sent by 20.02.1995. Camera-ready copy is due for 20.03.1995. DEMONSTRATIONS Demonstrations of generators, formal verifiers handling complete models, source code analyzers, translators of simulatable models into synthesizable ones are especially sought. Proposals for demonstrations should be submitted by 15.02.1995 to the Demonstration Chair. LOCATION Nantes can be easily accessed from Paris (two hours by TGV). Important Dates Submission deadline: 16.01.1995 Acceptance notification: 20.02.1995 Camera-ready copy due: 20.03.1995 Proposals for demonstrations 15.02.1995 General Chair Adam Pawlak, ARTEMIS/IMAG, Grenoble Adam.Pawlak@imag.fr General Vice-Chair Sylvie Hurat Thomson-CSF/SCTF, Orsay hurat@sctf.thomson.fr Program Chair Dominique Borrione ARTEMIS/IMAG, B.P. 53, F-38041 Grenoble Cedex 9 Phone: +33 76 51 43 04, Fax: +33 76 63 84 23 Dominique.Borrione@imag.fr Demonstration Chair Jean-Michel Berge France-Telecom, CNET-B.P. 98, F-38243 Meylan Cedex Phone: +33 76 76 43 35, Fax: +33 76 90 34 43 berge@cns.cnet.fr Local Arrangements Przemyslaw Bakowski IRESTE/Univ. of Nantes pbakowsk@ireste.fr P R O G R A M C O M M I T T E E Elfriede Abel, GMD Jim Armstrong, Virginia Tech Alessandro Balboni, Italtel Victor Berman, Cadence Nikil Dutt, U of California, Irvine Herbert Grnbacher, TU Vienna Marc Laurent, Matra MHS Oz Levia, Synopsys Stanley Krolikoski, Compass Paul Menchini, Menchini & Ass. Jean Mermet, ECSI and U Fourier Gabe Moretti, Intergraph Elect. Wolfgang Nebel, Oldenburg U Serafin Olcoz, TGI Jacques Rouillard, ESIM Steven Schulz, TI Eric Schutz, Alcatel Mietec Ronald Stewart, SGS-Thomson M. Alain Vachoux, EPFL Eugenio Villar, U of Cantabria Ron Waxman, U of Virginia Ron Werner, Motorola Alex Zamfirescu, Intergraph Elect. SUGGESTED TOPICS Component Modelling =================== VITAL models of ASICs Models of complex components Board-level simulation FPGA modelling Modelling styles for formally verifiable models Modelling styles for synthesizable models Modelling mixed digital-analogue components Experiences with analog HDLs Models reuse Legal issues ============ Proprietary rights Encryption of models Standards, conventions ====================== VITAL - Is it accurate enough? - Acceleration of VITAL primitives - Translation of existing libraries into VITAL models EIA-567 "VHDL Hardware Component Modeling and Interface Standard" WAVES - Test benches OPEN MODEL FORUM - Modelling of Standard Components Experience with libraries of Logic Modeling Swift Technology First experiences with VHDL-A OVI SDF, EIAJ ALR Tools ===== Model generators - Generators of libraries of cell models - Generators of complex models - Test bench generators Generation of models for different applications: simulation, synthesis, verification Efficient simulators (performance issue) Tools verifying correctness of models Quality assurance ================= Quality concepts and definitions Validation and certification of models Quality assessment Source code analysis