From: hohl@suffix.zfe.siemens.de (Andreas Hohl) Subject: VFE Spring '95 Call for Papers To: vfe@zfe.siemens.de (VFE Mail Reflector) Date: Wed, 5 Oct 1994 15:19:01 +0100 (MET) X-Mailer: ELM [version 2.4 PL24] Mime-Version: 1.0 X-UIDL: 781385596.006 CALL FOR PAPERS VHDL-FORUM FOR CAD IN EUROPE Spring '95 Working Conference IRESTE, Nantes, France - April 23 - 26, 1995 The VHDL-Forum for CAD in Europe (VFE) is the European users' group active in VHDL-related topics & standardization efforts and was founded at the International Federation for Information Processing (IFIP) conference VLSI '89 in Munich by IFIP WG 10.2/10.5. Since the founding of the IFIP/ECSI Special Interest Group on VHDL (SIG-VHDL) in spring '94 the VFE is supported by this group. The VFE members belong to an international range of companies, institutes, and universities. The VFE is open to all interested participants. The motivation and history of the group was the diverse European experiences in the field of hardware description languages and related topics. During the first two years, the main emphases of the VFE were the promotion and education of VHDL in Europe and the establishment of relationships to international VHDL users' groups (USA, Japan) and standardization groups. The VFE and the EuroVHDL conferences, as complementary, more research- oriented events, have built the European VHDL network with international connections. Both events, the EuroVHDL and the VFE, are going to be coordinated and organized under the umbrella of SIG- VHDL. The Spring '95 meeting focuses on user-oriented topics, because more and more European users are in the migration phase towards VHDL and have collected experiences in practise. Exchange of design experience is required, although the link between research and industrial application of VHDL is an important issue as well. Additionally, accompanying standards and standardized practises around VHDL have emerged during the previous year(s). VHDL-based tools, graphical entry, simulator backplane, cycle-based simulator, animator, standard modeling techniques for sign-off descriptions, synthesis with link to layout, hardware/software co-design promise better solutions for the users. What are the real benefits? These are topics to be addressed at the spring '95 working conference. Conference Secretary: IRESTE, La Chantrerie, CP 3003 44087 Nantes, France Phone: +33-40.68.30.79 Fax: +33-40.68.30.66 e-mail: pbakowsk@ireste.fr VFE-Board: D. Borrione, France, A. Hohl (Chair), Germany, J. Mermet, France, G. Musgrave, U.K., W. Nebel, Germany, S. Olcoz, Spain, F. Rammig, Germany, E. Villar, Spain. Program Chairperson: Przemyslaw Bakowski IRESTE, University of Nantes, France Local Organization: F. Bouchard, J. P. Caisso, J. F. Diouris, G. Ramstein Topics of Interest Authors are invited to submit original technical papers describing methods, tools, and design practices related to VHDL-based design. Topics include, but are not limited to: * Specification and modeling methodologies * Hardware/software co-design * Synthesis - from specification to layout * Experiences with the VITAL approach * Formal methods * High performance simulation * Complex component modeling * FPGA modeling * Complex ASIC design - PCB design * Test * VHDL in analogue design * VHDL front-end tools * VHDL back-ends * Tools and frameworks * Standardized practises * Use of VHDL in an industrial project * Impact of VHDL on design team organization * Non-standard applications (mechanical engineering, software engineering,...) The program committee wants to encourage especially the submission of papers describing the users' experiences with VHDL. In this case, full papers are not required for the proceedings. Requirements for Submission of Papers Authors should submit their papers to the Program Chairperson no later than January 16, 1995. Each submission should include a cover page and an extended abstract (4 pages), stating the major idea and scope of the presentation or the complete text of the paper in English, including all illustrations and references, not exceeding 12 pages. The one cover page should include: * Name, affiliation, and complete address for each author. * A designated contact person including e-mail, fax (if available), and phone number. * A designated presenter, should the paper be accepted. * The following signed statement: "All appropriate organ- izational approvals for the publication of this paper have been obtained. If accepted, the author(s) will prepare the final manuscript, i.e. a copy of the slides with an abstract, in time for inclusion in the proceedings and will present the paper at the conference." The 4 copies of the manuscript should include: * Title of the paper and a list of categories (given above), ordered by relevancy, most closely matching the contents of the paper. * Extended abstract or the complete text of the paper in English. Note: In case of papers describing the users' experiences with VHDL, full papers are not required for the proceedings, in other cases full papers are greatly appreciated. Notice of acceptance will be mailed to the contact person by February 17, 1995. Authors of accepted papers must sign a copyright release form. The final manuscript should be submitted by March 17, 1995. Panels, Tutorials, Working Group Sessions Proposals for topics for panels, tutorial sessions (half-day), and working group sessions must be submitted to the Program Chairperson no later than January 16, 1995. No proposal should exceed two pages in length. A description of the topic, structure of the session or tutorial, and a list of panelists should be included. Program Committee: P. Bakowski, IRESTE, France, A. Balboni, Italtel, Italy, D. Borrione, IMAG/Artemis, France, J.P. Caisso Matra-MHS, France, N. Dutt, University of California, USA, R. Burriel, Alcatel, Spain, H. Hegny, ANT Nachrichtentechnik, Germany, A. Hohl, Siemens, Germany, S. Krolikoski, Compass Design Automation, USA, S. Maerz, Siemens, Germany, J. Mermet, ECIP Office, Artemis, France, P. Miller, The ESDaEDA Group, U.K., G. Musgrave, Brunel University, U.K., W. Nebel, University of Oldenburg, Germany, S. Olcoz, TGI, Spain, A. Pawlak, GMD, Germany, P. Prinetto, Politecnico di Torino, Italy, F. Rammig, University of Paderborn, Germany, D. Sciuto, Politecnico di Milano, Italy, E. Villar, University of Cantabria, Spain. Please submit your completed manuscript to: Przemyslaw Bakowski, IRESTE, - VHDL-Forum, Spring '95 - , La Chantrerie, CP 3003, 40087 Nantes, France, Phone: +33-40.68.30.79, Fax: +33-40.68.30.66, e-mail: pbakowsk@ireste.fr Send your request to the VFE e-mail reflector vfe-request@zfe.siemens.de to be sure to be on the mailing list of the VFE.