Subject: November DASC Meeting Schedule (SUMMARY) To: stds.dasc@ieee.org Date: Mon, 17 Oct 1994 15:55:40 -0400 (EDT) IEEE Computer Society Design Automation Standards Committee Meetings in Conjunction with the Fall 1994 VHDL International Users' Forum The Ritz Carlton Hotel Tysons Corner, Virginia 17-18 November 1994 Thursday, 17 November 8:00 AM-5:00 PM VHDL Analog Extensions Working Group--P1076.1 Plaza room. 8:00 am-12:00 n VHDL Analysis and Standardization Group--P1076 Attache room. 8:00 am-12:00 n VHDL-EDIF Interoperability Working Group--P1165 Boardroom rm. 1:00 pm-5:00 pm VHDL Timing Methodology Working Group--P1076.4 Attache room. 1:00 pm-5:00 pm VHDL Parallel Simulation Study Group Consulate rm. 1:00 pm-5:00 pm System Design & Description Language Study Grp Boardroom rm. 5:30 pm-7:30 pm DASC Steering Committee Meeting & Plenary Session Plaza room. Friday, 18 November 8:00 am-12:00 n VHDL Shared Variables Working Group--P1076a Consulate rm. 8:00 am-12:00 n VHDL Synthesis Package Working Group--P1076.3 Boardroom rm. 8:00 am-12:00 n Open Modeling Study Group Ambassador rm 1:00 pm-5:00 pm Object-Oriented Extensions to VHDL Study Group Consulate rm. Subject: November DASC Meeting Schedule (Full Length) To: stds.dasc@ieee.org Date: Mon, 17 Oct 1994 15:55:40 -0400 (EDT) Ladies & Gentlemen, Here's the November DASC Meeting Scheule. --Paul -- Paul Menchini |mench@mercury.interpath.net|"Problems worthy of attack Menchini & Associates| voice: 919-990-9506 |prove their worth by 2 Davis Dr./POB 13036| pager: 800-306-8494 |hitting back." RTP, NC 27709-3036 | fax: 919-990-9507 | -- Piet Hein ------------------------------------------------------------------------------- IEEE Computer Society Design Automation Standards Committee Meetings in Conjunction with the Fall 1994 VHDL International Users' Forum The Ritz Carlton Hotel Tysons Corner, Virginia 17-18 November 1994 (Note: Due to the small number of groups meeting, no Saturday meetings are scheduled.) Thursday, 17 November 8:00 AM-5:00 PM VHDL Analog Extensions Working Group--P1076.1 Contact: Jean-Michel Berge, Chair +33 76 76 43 35 CNS-CCI +33 76 90 34 43 Chemin Du Vieux Chne-BP 98 berge@cns.cnet.fr MEYLAN CEDEX F-38243 FRANCE This meeting will take place in the Plaza room. 8:00 am-12:00 n VHDL Analysis and Standardization Group--P1076 Contact: Clive Charlwood, Chair 415-694-4307 Synopsys, Inc. 415-965-8637 [Fax] 700 East Middlefield Road crc@synopsys.com Mountain View, CA 94043-4033 This meeting will take place in the Attache room. 8:00 am-12:00 n VHDL-EDIF Interoperability Working Group--P1165 Contact: J. Bhasker, Chair 215-770-3983 AT&T Bell Labs 215-770-2773 [Fax] 1247 South Cedar Crest Boulevard, 2R242 jb7@mhcnet.att.com Allentown, PA 18103 This meeting will take place in the Boardroom room. 1:00 pm-5:00 pm VHDL Timing Methodology Working Group--P1076.4 Contact: Victor Berman, Chair 508-446-6276 Cadence Design Systems, Inc. 508-262-6777 [Fax] 270 Billerica Road berman@cadence.com Chelmsford, MA 01824 This meeting will take place in the Attache room. 1:00 pm-5:00 pm VHDL Parallel Simulation Study Group Contact: John Willis, Chair 507-253-8403 IBM Corporation willis@vnet.ibm.com 3605 Hwy. 52 North Rochester, MN 55901-7829 This meeting will take place in the Consulate room. 1:00 pm-5:00 pm System Design & Description Language Study Group Contact: Dave Barton, Chair 703-827-2606 Intermetrics, Inc. 703-827-2609 [Fax] 7918 Jones Branch Drive, Suite 710 McLean, VA 22102 dlb@hudson.wash.inmet.com This meeting will take place in the Boardroom room. 5:30 pm-7:30 pm DASC Steering Committee Meeting & Plenary Session Contact: Paul Menchini, Chair 919-990-9506 Menchini & Associates 919-990-9507 [Fax] 2 Davis Drive mench@mercury.interpath.net P.O. Box 13036 Research Triangle Park, NC 27709-3036 This meeting will take place in the Plaza room. Friday, 18 November 8:00 am-12:00 n VHDL Shared Variables Working Group--P1076a Contact: Steve Bailey 510-659-0901, x227 Vantage Analysis Systems, Inc. 510-659-0129 [Fax] 47211 Lakeview Boulevard sab@vas.com Fremont, CA 94538 This meeting will take place in the Consulate room. 8:00 am-12:00 n VHDL Synthesis Package Working Group--P1076.3 Contact: Alex Zamfirescu 415-691-6426 Intergraph Electronics 415-691-6061 [Fax] 381 East Evelyn Avenue azamfire@edaca.ingr.com Mountain View, CA 94041 a.zamfirescu@ieee.org This meeting will take place in the Boardroom room. 8:00 am-12:00 n Open Modeling Study Group Contact: Gabe Moretti, Chair 415-691-6434 Intergraph Electronics 415-691-9016 [Fax] 381 East Evelyn Avenue gabe@dazixca.ingr.com Mountain View, CA 94041 This study group has been proposed to the DASC Chair and will be discussed at the DASC Steering Committee meeting on 17 November. This meeting will take place in the Ambassador room. 1:00 pm-5:00 pm Object-Oriented Extensions to VHDL Study Group Contact: Doug Dunlop, Chair 703-827-2606 Intermetrics, Inc. 703-827-2609 [Fax] 7918 Jones Branch Drive, Suite 710 dunlop@wash.inmet.com McLean, VA 22102 This meeting will take place in the Consulate room.