Radio Free CAD CAE The Electronic Newsletter of the User Society for Design Automation ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Issue #2 14 March 1994 Published irregularly as a pipe cleaner for the USEDA mailing list. ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ [2.0 READ.ME] 2.1 JUST THE FAQ'S <37 Lines> USEDA E-mail addresses Current Officers of USEDA What's on the Cooker for 94? What will I miss if I can't make DAC 94? DUES Dos and Don'ts (You Don't, Yet) 2.2 BENCHMARKS <252 Lines> 2.2.1 Overview 2.2.2 DA Solutions VHDL and Verilog Simulation Benchmarks 2.2.3 SEVA Starts EDA Industry's First Comprehensive Product Evaluation 2.2.4 ESNUG 172 Editors Note The quality of this newsletter will be what you make of it. Newsletter questions, suggestions, or submissions to skmurphy@netcom.com Details as they unfold like an infinitely complex fractal origami. /SeanM [2.1 JUST THE FAQ'S] USEDA E-mail addresses useda@netcom.com (the CB Radio of the EDA Highway) moderated reflector to the USE/DA membership. useda-bod@netcom.com (ROpen Channel DS) reflects to the Board of Directors of USE/DA. useda-subscribe@netcom.com (Subscription Desk) request adds, deletes, help on mailing list. skmurphy@netcom.com (E-mail minion) send items for the Radio Free CAD CAE Newsletter. Current Officers of USE/DA Lone Ranger Jim King king@shula.enet.dec.com Tonto Sean Murphy murphy@cisco.com Banker Pat Pistilli pat@dac.coim Minister Mike Zeglin mzeglin@interim.com What's on the Cooker for 94? The four initiatives for our first year are: 1. Promote EDIF 3.0 as an interchange standard. 2. Define standard benchmarks for DA tools. 3. Define standard definitions for DA terms. 4. Define standards for DA business practices What will I miss if I can't make DAC 94? % Sign ups for next years initiatives at the USEDA/EDAC Booth. % A Birds of a Feather Session where Steve Schulz will provide a review of the USEDA Standards Survey, followed by a strategy session on next year's initiatives (Make suggestions at the USEDA/EDAC Booth). % A USEDA sponsored paper in the User Design Track on "Partnering with your EDA Vendor (A Twelve-Step Program: Co-Dependent No More)." DUES Dos & Don'ts (You Don't, Yet) There are currently no membership dues. Checks tendered at DAC '93 will be returned. For more info: Pat Pistilli (pat@dac.com), USEDA Treasurer. [2.2 BENCHMARKS] 2.2.1 Overview "When you can measure what you are speaking about, and express it in numbers, you know something about it; but when you cannot measure it, when you cannot express it in numbers, your knowledge is of a meager and unsatisfactory kind..." William Thompson, Lord Kelvin The American Heritage dictionary defines benchmark as "A standard by which something can be measured or judged" and synonyms for "a standard of comparison" as follows: test, measure, standard, mark, criterion, gauge, touchstone, and yardstick. In my experience you should always check the postmark on a benchmark, bear in mind it is the high-water mark of tool performance, and enclose it in quotation marks followed by a question mark if performed and supplied by the vendor. Three articles follow by recognized industry experts on benchmarking, none of whom are directly affiliated with the sales or marketing departments of any EDA vendors. Enjoy./SeanM 2.2.2 DA Solutions VHDL and Verilog Simulation Benchmarks Dave Wharton (DWharton@aol.com) DA Solutions Limited, formed last year by Roger Ball and John Hillawi, has teamed up with David Wharton to compare the performance and functionality of digital simulators. The exercise will cover all the major simulation offerings in VHDL and Verilog HDL. DA Solutions will establish a series of benchmarks for simulation at different stages of the ASIC design flow. The purpose is to measure impartially the functionality and performance of each simulator when used by a real designer. The benchmark suite contains both public domain circuits and real ASIC designs provide by ASIC end users. Companies and engineers with VHDL or Verilog HDL circuits can submit circuits to be included into the benchmark suite. This could be done under a confidentiality agreement if necessary. Circuits from designers are chosen to represent different architectures and gate counts. DA Solutions will use Processor, Telecommunication, Graphics/DSP and more unstructured implementations. They have acquired and written VHDL and Verilog HDL descriptions at behavioral, RT and gate levels to measure performance and capacity of simulators running very large circuits. The goal is to collect sufficient information on the features and capabilities of simulators to help ASIC and System designers to select the best tool for their own application. EDA Vendors are very supportive and have offered software and support. VI, OVI and EDAC have all been discussing the need for benchmarking. They are considering recommendation of this benchmark suite. Publication of results will be in the second half of the year as a detailed report. For comments, more information, or to be notified when the report is available, please contact: David Wharton (Dwharton@aol.com), DA Solutions. [Editors Note: What follows is a summary of a presentation Dave Wharton made to USEDA] Objectives % Provide an ongoing, vendor independent view of simulation products % Characterize both simulation functionality and performance % Provide an industry standard simulation benchmark suite % Provide an ongoing comparison of VHDL and Verilog technologies % Extend, later, to other aspects of ASIC design HDL Simulation suite % Where possible, published with testbenches to ensure acceptance % Independently run to ensure accuracy and impartiality % Available to both EDA vendors & ASIC designers % A supported product (e.g. VHDL-93, OVI 2.0) Benefits to EDA vendor % Exact comparison of vendor's product with the competition % Assists in differentiating the product % Measures internal engineering progress Benefits to ASIC designer % Reduces the cost of tool evaluation % Eliminates 'non-working' products and 'wrong-for-application' products % Avoids developing internal benchmarks % Improves tool purchase and set-up time % Allows designer to select leading edge tools faster Stages of the Design Process % Behavioral description input and simulation % RTL input and simulation % Interactive capability and speed % Rapid design changes % Gate level simulation % Capacity, accuracy and speed Benchmarks: VHDL group % Network benchmark, behavioral, variable size % Viper benchmark, behavioral model of ASIC % Processor benchmark, behavioral/RTL design % Combinatorial benchmark, gate, variable size % Sequential benchmark, gate, variable size % Crusher benchmark, gate, DoD 80k circuit Benchmarks: Verilog suite % RTL version of MIPS Processor system % RTL version of ATE pin channel % Behavioral model of communications processor % LFSR circuit, RTL and gate implementations % Additional Verilog gate level circuits Comparison Metric % Compiler features, interactive and batch % Run time debug, source debug % User interface features % Links to other EDA tools % ASIC libraries % Compilation and simulation execution times % Memory occupancy % Price and availability Exercise Plan and Funding % Simulation Exercise timing - Q1/Q2, 1994 % Deliverables - Exercise reports for EDA vendors and ASIC end users % Exercise Pricing % Majority of 94 funding provided by EDA vendors % Some funding by Report sales Companies targeted for involvement: Cadence Design Systems, Chronologic Simulation, GenRad, Frontline, IKOS Systems, Intergraph, Mentor Graphics, SimuCad, Synopsys, Systems Science, Viewlogic/Vantage, and Zycad. 2.2.3 SEVA Starts EDA Industry's First Comprehensive Product Evaluation Yatin Trivedi (trivedi@netcom.com) Larry Saunders (lfs@mcimail.com) San Jose, CA-- February 9, 1994 -- Seva is working with ASIC & EDA Magazine to perform a series of product and technology evaluations and benchmarking services for the ASIC and EDA markets. Seva, in association with ASIC & EDA, will initially review several Verilog and VHDL based design automation tools. A summary of the results and the methodology used by Seva in evaluating design automation tools and ASIC technologies will be published in the upcoming issues of ASIC & EDA. Seva, with headquarters in San Jose, California, provides project management, hardware and software design and consulting, training, and product and technology evaluation services to the ASIC and EDA industry. Seva's project management expertise and the use of global resources allows customers to meet their time to market goals in a cost efficient manner. Seva agreed to do product reviews because prod- uct evaluation data is not readily available to the end user. Every user has to go through the pain- ful and costly process of evaluating new tools and methodologies prior to acquiring these tools. "Comprehensive evaluation criteria do not exist in the industry. Neither vendors nor users are satisfied with rankings based only on performance. They do not provide useful information to the user in product selection. The total cost of ownership is more important than just the performance," said Yatin Trivedi, principal and co-founder of Seva, and a leading authority on Verilog HDL. Trivedi is co-author of the book Digital Design and Synthesis and is an active member of Open Verilog International. "We have been users of these tools and during our numerous consulting assignments have helped our customers identify their design automation tool needs, and we assisted them in the tool evaluation and selection process," said Larry Saunders, principal and co-founder of Seva and noted VHDL columnist for ASIC & EDA. Saunders is founder and past chairman of the VHDL User Forum and an active member of VHDL International. Lindsey Vereen (lindsey@asic.com), Editor-in-Chief of ASIC & EDA, commented: "We selected Yatin and Larry to perform product evaluations because of our high regard for their technical skills as well as their integrity, independence, and strong advocacy of user interests." Seva evaluations will include more than just raw throughput: language compatibility with Language Reference Manual, integration of tools with other environments, ease of use for debugging, and Rround-tripS time among many criteria developed in cooperation with real designers. Performance will be measured using the Seva Evaluation Index, a proprietary 3D cube evaluation method established by Seva. Yatin Trivedi added a postscript: Seven PC based Verilog simulator companies are: Simucad, Wellspring Solutions, Intergraph, Frontline Design Automation, Fintronic USA, CAD Artisan, Automata Publishing. The summary of this evaluation will be pub- lished in the April 1994 issue of ASIC & EDA and a detailed report will be published and made available by Seva. We did not include Chronologic and Cadence because their simulators run on workstations, and they are most widely known companies. With new push towards PC based designers and FPGA designers using simulation and HDL methodologies, reviewing PC based simulators was seen more appropriate. There is no reason why the same criteria cannot be applied to VCS and Verilog-XL products, however, performance number comparison should be avoided until a relationship between 486,DX2,66 and SPARC-10 can be established clearly. For VHDL we have invited 11 vendors. We do not know how many will participate: Cadence, Viewlogic, Synopsys, MTI, Zycad, Mentor, SEE Tech, Redwood, Aldec/Susie, Ikos, HUM. VHDL evaluation will take place both on PC and workstation. The performance results will be shown separately. What USE/DA members can do is to suggest what criteria they might like us to include in the evaluations, and give additional examples to cover broader spectrum of models and methodologies. I appreciate your comments, Yatin Trivedi. 2.2.4 ESNUG 172 Editors Note jcooley@world.std.com (John Cooley) ESNUG Post 172 (20 Jan 1994) [What follows in NOT a paid advertisement. I've received no money, no sexual favors,:^(, no noth- ing from anyone for this; it's purely my own personal professional opinion. - John Cooley] ESNUG Editor's Note: I would like to publicly applaud Chronologic Simulation's approach to doing business. Most EDA vendors put special clauses in their licencing agreements to forbid customers from doing comparative benchmarks on their software. Also, most EDA vendors *say* that the vast majority of their customers are repeat customers, they have very few bugs in their products and those bugs they do have are fixed quickly -- you know, the usual happy customer marketing drivel that's unconfirmable and perfect for salesmen to use to convince you to buy their products. In contrast, Chronologic Solutions actively encourages everyone to benchmark their products. Now they're offering an upgrade from Verilog-XL to their high speed Verilog simulator (VCS) for what works out to be $5000 ($1000 plus $4000 maintenance) with a limit of one upgrade per engineering lab. Through these *actions* Chronologic is clearly showing that the vast majority of their customers are repeat customers. They don't make money selling at this price; their *actions* show they're confident they'll make money when you return to buy a *second* VCS licence. They don't have a large aggressive sales staff out to give you the hard sell; they let the benchmarks speak for themselves. Also, because Chronologic is a small company; you're not four bureaucratic layers away from the guy who wrote the code when you report a problem. Overall, I see this as a company of engineers who wanted to make a screaming fast Verilog simulator -- not businessmen out to make a quick buck in the EDA industry. Because Chronologic Solutions sells, in my opinion, a well supported kick-butt Verilog simulator, I'm recommending you take advantage of this upgrade offer before the January 31st deadline. They're at 1-800-VERILOG. Synopsys VSS 1.0 # Mentor 1.1 # Viewlogic 2.0 ## Silicon Auto 2.1 ## Cadence Turbo 3.5 #### Vantage 4.1 #### Model Tech 4.1 #### Cadence Leap 5.4 ##### Simucad SILOS 5.6 ###### Racal-Redac 8.3 ######## Chronologic 27.0 ########################### Relative Speed Benchmark of HDL Simulators (June 14, 1993 EE Times) John Cooley is an EDA & ASIC Design Consultant who manages the Electronic Synopsys User Group (ESNUG). You can subscribe by sending E-mail to jcooley@world.std.com End of Issue #2 of RADIO FREE CAD CAE 14 March 1994 The Electronic Newsletter for Users of Electronic Design Automation Email useda-subscribe@netcom.com to subscribe