Date: Wed, 18 May 1994 06:20:17 -0700 From: skmurphy@netcom.com (Sean Murphy) Subject: Radio Free CAD CAE (Issue #3) To: rfcc-subscriber@netcom.com Radio Free CAD CAE The Electronic Newsletter for Users of Electronic Design Automation ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Issue #3 11 April 1994 An On-Line-Zine published irregularly as a USEDA E-Mail pipe cleaner ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ [3.0 READ.ME] 3.1 JUST THE FAQ'S <58 Lines> 3.1.1 USEDA E-mail addresses 3.1.2 Current Officers of USEDA 3.1.3 USE/DA The User Society for Electronic Design Automation 3.2 INTEROPERABILITY 3.2.1 EDAC Interoperability LAB <129 Lines> 3.2.2 CFI Study: Cost of Interoperability <16 Lines> 3.2.3 EDIF PCB Update <108 Lines> 3.3 E-Mail to the Editor 3.3.1 Please Remove My Name <54 Lines> This issue has an interoperability focus and our first E-mail to the editor (see section 3.3.1). As Jim King details in 3.1.3: we've got good stuff set for DAC 94: Come Catch the Wave! If you would like to help staff the USEDA booth contact: Steve Roman (smroman@ihpds1.att.com) at +1 708 979 1791 As always, RFCC will be what you make of it: questions or suggestions to skmurphy@netcom.com. Details as they impact our event horizon like tachyons from a black hole... /SeanM [3.1 JUST THE FAQ'S] 3.1.1 USEDA E-mail addresses useda@netcom.com (the CB Radio of the EDA Highway) moderated reflector to USEDA membership. useda-bod@netcom.com ("Open Channel D") reflects to the Board of Directors of USEDA. useda-subscribe@netcom.com (Subscription Desk) request adds, deletes, help on mailing list. skmurphy@netcom.com (E-mail minion) send items for the Radio Free CAD CAE Newsletter. 3.1.2 Current Officers of USEDA Prexy Jim King king@shula.enet.dec.com Veep Sean Murphy murphy@cisco.com Treasurer Pat Pistilli pat@dac.com Secretary Mike Zeglin mzeglin@interim.com 3.1.3 USE/DA: The User Society for Electronic Design Automation by James King (king@shula.enet.dec.com) Date: Wed, 23 Mar 94 15:14:22 EST reprinted from EDAC Newsletter The environment in which EDA Users work today involves multiple EDA tool suppliers on multiple hardware platforms. USE/DA will address the problems and issues that stem from this multi-vendor environment. We will provide the voice of the customer in the form of focused and constructive feedback that will highlight what we need to be successful and what we are depending on from the EDA industry. The goals of USE/DA are to create two-way communication between the EDA Vendors and the EDA Users, to create a strong and unified voice of the needs and issues of EDA Users, and to provide pro- active EDA User support for the Design Automation Conference. The first step in implementing the communication goals between USE/DA and EDAC is to place representatives on each other's respective Boards of Directors. Tom Pennino is the EDAC representative on the USE/DA Board of Directors and Sean Murphy is the USE/DA representative on the EDAC Board of Directors. This year USE/DA initiated a membership newsletter that is broadcast over Internet. To create a unified picture of USER needs and issues we have commissioned our first Survey and focused it on EDA Standards. The results of the survey have been evaluated will be published in a report this summer. The goal has been to access the understanding and impact of EDA Standards from a User's viewpoint. The results prioritize the reasons that EDA Standards are important, what Standards are considered critical, and how long it would take for Users to change vendors if they do not support standards. We are sponsoring the following activities at DAC this coming year. We will conduct our annual membership meeting where we will review the results of the Standards Survey and initiate programs to explore specific topics in detail, we will present a paper in the user track titled "Partnering with EDA Vendors", and we will have a USE/DA booth to distribute USE/DA information and sign up new members. [3.2 INTEROPERABILITY] 3.2.1 EDAC Interoperability Lab Walter Haefeker <76456.3236@CompuServe.COM> Date: Mon, 20 Dec 93 11:17:21 PST Subject: EDAC Interoperability Lab To: useda-bod@netcom.com I am Chairman of the Steering Committee for the EDAC Interoperability Lab. The attached proposal was adopted at the last EDAC Executive Council Meeting. I am currently looking for users to become involved in my committee to represent the user communities interest and provide input from that perspective. Please take a look at our proposal. I am looking forward to your feedback. Objective The objective of the EDAC Interoperability Lab is to ensure continued growth and an improved image of the EDA industry by providing all EDA vendors controlled access to each others tools for developing and testing the interoperability demanded by end users at a neutral facility capable of administering access. Proposal End user environments usually include a variety of tools from multiple EDA vendors, often including emerging companies. Recognizing this need, major EDA vendors such as Mentor Graphics and Cadence have established the Open Door and Connections programs designed to facilitate integration into environment of the major vendor at the technical and marketing level. The complex rules and procedures established in these programs make getting access to tools for interoperability testing with a broad range of products an almost impossible task for most vendors. The process of providing access to a large field of 3rd parties creates administrative and security problems. In the spirit of helping the industry to grow through improved interoperability and "open systems," in a way that complements the ISV programs instituted by most major vendors, the Emerging Companies Committee proposes that EDAC support the establishment of an EDAC Interoperability Lab at the Center for Software Development. Each EDAC member will be asked to provide a license to the Center for each of their products and training for a member of the Center's staff on installation and maintenance procedures for the products. Vendors are encouraged to provide a technical contact as well as a contact for questions of access and 3rd party relations along with their tools. To increase and maintain a high level of interoperability of EDA tools, the industry needs to improve the flow of information about software revisions that can affect interoperability with other vendors. To facilitate peer to peer communications among vendors in the area of interoperability, either the Center or EDAC will establish a directory of EDA products, including release and technical contact information. EDAC will establish a committee consisting of representatives of major and emerging EDA vendors as well as end-users to oversee the administration of the lab as well as define common rules of access to the tools to ensure that the tools provided are used only for the purposes intended here. Neither the center nor the vendors can handle this process for all tools at once. The committee is going to identify product categories that have the greatest need for interoperability and issue a "call for software" for that specific area. Examples of likely candidates are design frameworks and tools that use EDIF. The EDAC Interoperability Lab is intended to complement the efforts of standards organizations such as CFI or EDIF, and will provide the infrastructure to accelerate the implementation of standards. ECC is in close contact with those standard organizations since they are going to be major beneficiaries of the lab. The lab will make it easier to test for compliance and interoperability among tools that support standards. Background The Center for Software Development is a not-for-profit organization chartered to help software companies bring higher-quality products to market more rapidly. It is a new organization, having started operations in April 1993 and enjoying a highly successful Grand Opening on June 25, 1993. Despite the newness, the positive impact of the Center is already being felt. Small and large companies alike are using the Center. Some of the larger companies using the Center for software QA are Apple, JVC and Xerox. As of this writing ten products (from Pixar, T/Maker and Future Labs) have been released that were tested at the Center. Errors were found at the Center that would not have otherwise been caught. The Center has independent multivendor labs for self-service testing. Developers can use either the Walk-in Lab for access to PCs, Macs and UNIX workstations in standard configurations or the Custom Labs for complex, specialized or secure configurations. The Center's current resource list includes pen computers, PCs, Macs, UNIX workstations, operating systems, development tools, printers, plotters and networks. Cost There is no cost to EDAC or its member companies to build an EDAC Interoperability Lab other than the cost of providing their products and possibly the cost of a staff member to install and support the tools. Hardware and software vendors will provide the necessary platforms. Users of the lab will pay the standard usage rates in effect at the Center. The Center is in full operation and has already established relationships with the major hardware platform vendors. It either has or will have the hardware and operating systems necessary for EDA testing. The essential ingredients now missing are 1) EDA software licenses from EDAC members; and 2) communication channels with EDA software developers. While EDAC could theoretically establish a lab elsewhere, the cost and expenditure required just to get to the point where the Center is now would be prohibitive. Implementation An example of a similar action by EDAC can be seen in EDIF. With EDAC's acceptance of this proposal and communication with its members as to the importance of supporting this effort, the Center will be able move forward quickly by leveraging the resources that are already in place. The Center will "drive" this effort and make the EDAC Interoperability Lab a reality. Conclusion The result of EDAC's efforts will be a lab of tremendous value to the industry. It will no doubt require some significant effort to build the EDAC Interoperability Lab, but this is the type of opportunity that the ECC, EDAC and the Center were formed to meet. Postscript - 22 Mar 94 We have the attorneys reviewing the legal framework we have defined in the steering committee. This should be completed in a few more weeks. We should be able to start getting the first software packages in shortly after that. I will keep you posted. 3.2.2 CFI Study: Cost of Interoperability by Perri Wickham Date: Mon, 28 Mar 94 The CAD Framework Initiative (CFI) is conducting a research study to determine the cost and impact of better interoperability among EDA tools. Collett International has been contracted to conduct the study.Participation in the study requires the completion of an 8-page questionnaire. Answers will be held completely confidential: individual company data will not be disclosed, only the aggregate results from participating companies. Results of the study will be presented at the upcoming EII '94 Conference to be held May 4 - 5, 1994, in Oakland, California. If you are interested in participating in the research study, please email perri@cfi.org with your name, address, and fax number or call CFI at (512) 338-3258. 3.2.3 EDIF PCB Update by James H. Clark (clarkj@cup.portal.com) Date: Tue, 29 Mar 94 During the recent EDIF steering committee meeting in San Diego many issues were discussed including EDIF's plans to develop an EDIF PCB format in 1994. Why EDIF PCB? The Electronic Tools Company (ETC) feels that there is a need to have an EDIF format for PCB's. We feel this way because there remains a real requirement to transport PCB layouts from one CAD system to another and EDIF PCB can help to eliminate many of the problems that are regularly encountered during this process. At the present time, the industry is using a rather expensive mix of software to handle the interfacing of PCB data. Software that often has a high initial selling price and later on requires expensive maintenance and upgrades. We have yet to mention the added work on the part of the engineer to assure the accuracy of the translation. This added work usually results in making manual corrections that delay the completion of the translation and ultimately, delays the final production of the PCB. Almost always, this increases the overall cost. The EDIF PCB format is being developed to make this entire process easier, more reliable, and less costly. EDIF and Portability Portability and EDIF quite often are synonymous in the minds of electronic designers! EDIF was created for the interchange of electronic design data between different systems (CAE/CAD, manufacture, test and others) in some electronic way, e.g. file transfer by tape or network. Many of the same arguments for exchanging schematic and connectivity data prior to the formation of EDIF are still in effect for today's PCB designers. The added PCB tasks involving board layout, layout analysis, and post processing present an even greater challenge for EDIF PCB. Portability of these later tasks many times is a necessity in order to continue on with manufacturing, assembly and final testing. Back at the time of the origin of EDIF there were a broad range of interchange formats and hardware description languages many of which were limited to specific companies and specific types of design data. Moving from one standard to another was difficult as well as using any combination of tools from different vendors. This dilemma is what brought about the need for EDIF and has made it the most widely used electronic design interchange format in the world today. By the time this article is distributed EDIF will have announced the shipping of EDIF Version 3 0 0. EDIF 3 0 0, will solve many of the discrepancies and limitations that presently exist in EDIF 2 0 0. EDIF 3 0 0, incorporating information modeling, introduces explicit bus constructs, simplified rippers, explicit definition of view-wide connectivity, a more explicit key word structure, clearer instantiation and removal of cell overloading. These and other reasons, but most importantly the information modeling that now exists, makes EDIF Version 3 0 0 an ideal format to draw upon when the work on EDIF PCB is started. The findings of the EDIF PCB technical sub committee (EDIF PCB TSC) also supported the reasons for why EDIF PCB should be developed. The charter of the EDIF PCB TSC was to address all aspects of the EDIF standard that affect printed circuit board logical and physical design, manufacturing, assembly and test. Not only the PCB layout graphics have to be modeled but generally accepted concepts like padstacks, footprints, and others must be considered. The European Group and the US Group making up the EDIF PCB TSC, have produced a conceptual model (using the EXPRESS Information Modeling Language) that will later be integrated with the EDIF EXPRESS Information Model. It is felt that use of an EXPRESS information model for EDIF PCB is the best way to outline in detail and come to agreement on PCB related concepts in preparation for EDIF syntax crafting. How have we gotten along for such a long time with out an EDIF PCB format? There are in existence today several formats used in the PCB design interface process. A real understanding of the purpose behind each of these various formats is the key. Each was brought about with specific objectives in mind but we do not believe that the formats being used today in the PCB environment were developed with true portability in mind. By true portability we take into account all of the following factors: a) widespread usage of the format by many different vendors with varying hardware platforms. b) high reliability through accurate portability giving more confidence to the end user. c) easy to write to and read from, d) minimization of cost because of higher development efficiencies, and e) a wider scope of capability/flexibility for the end user. EDIF has demonstrated true portability and it appears they have continued the same with EDIF Version 3 0 0 and will with EDIF PCB. Why has EDIF not addressed a PCB format sooner? EDIF has been completely involved with an extensive effort to create the best, most widely accepted format in existence for ASIC and integrated circuit design. They have spent the majority of their time accomplishing this task. Developing EDIF 2 0 0 and now EDIF 3 0 0 while at the same time offering quality support has been a significant accomplishment. The recent origination of the EDIF Technical Center located at the University of Manchester, England is a prime example. The Center provides crucial technical support to EDIF users by means of an electronic mail service, frequent tutorials and other awareness activities. The Center also serves as a repository of EDIF test data, software and related documents. The Technical Center works closely with the EIA/EDIF organization to ensure that users are informed about this service. EDIF has planned what it can successfully accomplish extremely well. EDIF PCB has been planned for implementation later in 1994 and once again (funding permitting) is expected to meet this schedule. For more information on funding EDIF PCB contact: Electronic Industries Association 2001 Pennsylvania Avenue, NW. Washington, DC. 20006 Attention: Patti Rusher, Director or email: 0005446089@mcimail.com James H. Clark is Vice President Marketing for the Electronic Tools Company. [3.3 E-MAIL TO THE EDITOR] 3.3.1 Please Remove My Name Date: Wed, 16 Mar 94 09:13:25 EST From: vhdl!wdb@uunet.UU.NET (William Billowitch) To: skmurphy@netcom.com Dear Sean: I read your first newsletter. I am afraid that the tongue-in-cheek style in which the newsletter is written makes, at least this reader, discount the credibility of what you are trying to accomplish. The ESNUG is also written in this style and most professionals who have been around for more than five years and take other than the us-vs-them angle on problem solving need something a bit more seriously oriented. Please remove my name from your distribution list. Sincerely, William Billowitch Date: Thu, 17 Mar 1994 08:49:49 -0800 Dear Bill: You are not currently on the distribution list for Radio Free CAD CAE. I believe you read a "preview copy" of issue #2 that Steve Schulz, a USE/DA board member, forwarded to the VITAL/VI mailing list. This preview copy for issue #2 is only 1/4 the size of the full issue and did not contain any of the text of the SEVA or DA Solutions benchmark initiatives or the ESNUG Editorial reprint. To allow you to better assess the intent of USE/DA I am forwarding you both the first issue and the full text of issue #2 under separate cover. I have spent more than a dozen years in the EDA industry working both as a user and as a vendor. Everyone on the USE/DA board has spent at least five years in the industry: I think our credibility will ultimately be assessed by what we accomplish or fail to in the next six to 18 months. While Mr. Cooley is sometimes tongue-in-cheek I find his ESNUG newsletter very informative, in the "Editors Note" that he graciously allowed us to reprint I believe that he is writing very seriously on the value of standard benchmarks for the EDA industry, in particular their positive impact on EDA business practices. I would suggest, given your interest in VHDL technology and your more than five years experience in the EDA industry, that either the DA Solutions or the SEVA (or both) simulation benchmark initiatives could benefit from your advice and support. I am also very interested in what magazines, newsletters, email-reflectors you find useful or informative. I will not put you on the list unless you request it via the useda-subscribe@netcom.com alias./SeanM End of Issue #3 of RADIO FREE CAD CAE 11 April 1994 The Electronic Newsletter for Users of Electronic Design Automation Email useda-subscribe@netcom.com to subscribe