Development of a standard simulation and related tools interface for component models written in VHDL, Verilog, C, and other description languages.
To provide a standard method for interfacing and managing complex electronic models to design automation tools. This method is aimed at providing efficient, accurate, and tool independent interfaces suitable for large designs such as systems on a chip.
Specifications, Documents, and Papers
The official specification for this IEEE standard must be obtained from the IEEE. Please check www.ieee.org for information.
Having finished its work toward the approval by RevCom of P1499 as an official IEEE Standard, the Working Group is resting. The next meeting is planned in conjunction with HDLCon, April 6-9, 1999 in Santa Clara. A notice with the actual place, time and date will be sent to the reflector as soon as the date is known.
There will be a meeting during the week of April 5 in Santa Clara California in conjunction with HDLCon
Technical Committee Meeting Minutes
To examine the current set of meeting minutes for the technical committee, follow here
To subscribe to the email reflector send mail to: omf-request@vhdl.org
To become a member of the P1499 Technical Committee send mail to: Doug Dunlop Technical Committee Chair
To learn more about the OEC send mail to: Will Hobbs, OEC Chair
IEEE OMF Committee Chair: Gabe Moretti
Last updated February 1, 1999
