-------- Original Message --------
Subject: [sv-ac] Erratta on implication operator.
Date: Tue, 26 Aug 2003 09:02:57 -0500
From: Adam Krolnik <krolnik@lsil.com>
To: sv-ac@eda.org



Good morning;

I have an erratta concerning the implication operator.

To this list of points in 17.7.11, I would like to add the following before the last
point (which may be removed pending other proposals.)


WAS:
<nothing>

Proposed:

o Only zero or one match of the consequent sequence_expr will occur. There is an
implicit first_match operator applied to the consequent. For example.

  antecedent_expr |-> consequent_expr

is really evaluated as:

  antecedent_expr |-> first_match (consequent_expr)


There is a reference to this in section 17.10 (pg 176.) but it should be explicitly
noted here next to the operator, in addition to the section on properties.

     Thanks.

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074