Minutes of the November 15, 2004 SV-BC Meeting (Design Modeling Committee) 10212 Day 58517 11110 Month 11009 00000 Year 44444 aaaaa Matt Maidment - Intel aaaaa Brad Pierce - Synopsys aaaaa Karen Pieper - Synopsys -aa-a Dan Jacobi - Intel -aaaa Dave Rich - Mentor Graphics aaa-a Francoise Martinolle- Cadence aaaaa Mark Hartoog - Synopsys -a-aa Rishiyur Nikhil - Bluespec -aaaa Cliff Cummings - Sunburst Design aaaaa Steven Sharp - Cadence aaa-a Stuart Sutherland - Sutherland HDL aaa-a Don Mills - LCDM Engineering a-aaa Logie Ramachandran - Synopsys aaaaa Surrendra Dudani - Synopsys aaaa- Doug Warmke - Mentor Graphics aaaa- Kathy McKinley - Cadence from 1364 ETF ---a- Steve Dovich - Cadence -aaa- Greg Jaxon - Synopsys a-a-- Jonathan Bradford - Micronas Agenda: +The IEEE patent policy was reviewed http://standards.ieee.org/board/pat/pat-slideset.ppt +Review minutes of the previous meeting: http://www.eda.org/sv-bc/minutes/sv-bc_04_11_08.txt Stu moves to accept the minutes Brad seconds Motion Passes. +Review 1st Draft of Datatype on Nets WG Surrendra believes that classes and chandles should be excluded from the data type/value definitions. Feedback was noted. WG would benefit from more specific feedback from Surrendra on where these concepts conflict. The term "type" is used in many places in the LRM and needs to be updated. Usage might refer to a net type or a data type. A global, editorial change would be most efficient, but the proposal attempts to address the bulk of these issues. Logie asked if syntax should be backward compatible with Verilog. Steven & Kathy replied that the syntax is backward compatible Verilog. For SystemVerilog, this is true as well, except for assignments between an array of wires and arrays of variables. Under the proposal the rules would be more strict, but the result is more consistent assignment rules. Someone asked if the LRM refers to structs a collection of variables. Kathy replied that the WG attempted to address this where it was identified. If these changes are adopted then the BNF would benefit from some alterations to match the new terminology. Brad thought this could be done as a final step of the process. The WG prefers that net data types be defined as "4-state bitstream type", but they identified a problem with the current bitstream type definition that prevents this. Dave Rich agreed to pursue this problem. Matt asked if sensitivity derivation is affected by these changes? Steven believed net objects should be no different than variables. The benefits of data types on wires were summarized as: + bi-directional objects with SV data types + driver resolution extended to objects with SV data types + timing back-annotation to objects with SV data types The group generally agreed that further work on this proposal should continue. Group agreed that the deadline for submitting detailed feedback is Nov 17. WG will meet on Nov 18 and next draft should be available shortly thereafter. Mark asked if it was possible to see a draft of the LRM including these changes to review in full context. Based on current LRM draft schedule this is not feasible before December 1. Brad asked that the keyword 'var' be added to variable declaration syntax. This would be an optional modifier of variable declaration and provides a sort of symmetry between net and variable declartions. Action Items Completed 11/08/04 Matt Confirm Nov 15th net data type review meeting time with Karen Pieper & Steven Sharp. 11/08/04 Matt Add recent minutes to SV-BC web page 11/08/04 Brad Notify Matt when proposal for 223 is updated (Brad reports this is not a bug and should be put to a vote). Pending 09/27/04 Steven Review 221 for possible inclusion in immediate priority issues to be resolved. 10/11/04 Dave Related to 157, File new errata for continuous driver (assign) 11/08/04 Matt Send out tentative meeting schedule through Dec 1.