Minutes of the January 31, 2005 SV-BC Meeting (Design Modeling Committee) 

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aaaaa Matt Maidment       - Intel               
aa-aa Brad Pierce         - Synopsys 
aaaaa Karen Pieper        - Synopsys           
-aa-a Dan Jacobi          - Intel              
a--aa Dave Rich           - Mentor Graphics     
aa-aa Francoise Martinolle- Cadence              
aaaaa Mark Hartoog        - Synopsys  
a-aa- Rishiyur Nikhil     - Bluespec
a-aa- Cliff Cummings      - Sunburst Design 
aa--a Steven Sharp        - Cadence                   
a-aaa Stuart Sutherland   - Sutherland HDL 
aaaaa Don Mills           - LCDM Engineering 
---aa Logie Ramachandran  - Synopsys                      
aaaaa Surrendra Dudani    - Synopsys 
a-aa- Doug Warmke         - Mentor Graphics 
aaaaa Kathy McKinley      - Cadence            
a--aa Greg Jaxon          - Synopsys              
a-a-- Jonathan Bradford   - Micronas              
a---- Tom Fitzpatrick     - Mentor Graphics

Agenda:

+Review IEEE patent policy
  http://standards.ieee.org/board/pat/pat-slideset.ppt 

The patent policy was reviewed.

+Review Previous Meeting Minutes
  http://www.eda.org/sv-bc/minutes/sv-bc_05_01_17.txt

Brad moves to accept the minuts.
Kathy seconds.
No opposed.
Abstain: Cliff, Jonathan, Nikhil
Motion Passes.

+LRM Review
 
 168: 
  http://www.eda.org/sv-bc/hm/2672.html

Kathy pointed out conflicts with other changes in 2 section, 23.7 & 3.7.

For the conflict in 23.7:

Replace:
        SystemVerilog provides system functions to return information about 
        a particular dimension of an array object (see Clause 4) or integral 
        type (see 3.3.1) or data type. 

With:

        SystemVerilog provides system functions to return information about 
        a particular dimension of an array (see Clause 4) or integral (see 
        3.3.1) data type, or data objects of such a data type. 

Kathy Moves to accept this proposal.
Brad Seconds.
Opposed: No.
Abstain: No.
Motion Passes.

For the conflict in 3.7

Replace:

    SystemVerilog includes a string data type, which is an ordered 
    collection of characters. 

With:

    SystemVerilog includes a string data type. A value of the string 
    data type is an ordered collection of characters. 

Nikhil moves to accept the proposal.
Kathy seconds.
No Opposed.
No Abstain.
Motion Passes.

AI: Brad add these as 1 new item in SVDB.

356

Brad moves to accept submitted proposal
(http://www.eda.org/svdb/bug_view_page.php?bug_id=0000356)

Dave seconds
No Opposed. 
No Abstain.
Motion passes.

357

Brad moves to accept the proposal with the friendly amendment to:

Replace:

 the same length for each of those dimensions

With:
 
 the same number of elements for each of those dimensions

Dave seconds.
No Opposed. 
No Abstain.
Motion Passes.

 315:
  http://www.eda.org/sv-bc/hm/2666.html
 
In sections 17-17 and a.1.5, change the bind_target_scope production
as follows:

   bind_target_scope ::=
       module_identifier
     | interface_identifier


Doug moves to accept this proposal.
Surrendra seconds.
Opposed: Dave Rich (opposed to LMR disallowing instances in programs)
No Abstain.
Motion passes.

254:
 http://www.eda.org/sv-bc/hm/2655.html

Brad updated issue 254 to include background on issues that remain
open despite the efforts of 254 (see background_on_254.htm).  Brad 
also  proposed a solution (see correspondence_expressions.htm).

Brad reviewed the background motivation and presented the proposed
fix, correspondece expressions.  Issues with the proposal were 
identified but no resolution could be identified before the
end of the meeting.  In an effort to address these issues:

Some members of the sub-committee will meet informally on Monday, 
January 31, 1:30pm PST.  That group should generate another
revision of the proposal.  That revision will be presented in a
continuation of the SV-BC meeting, on Tuesday February 1, 10am PST.

From Tuesday, February 1, 10am PST.

As currently defined, these expressions can be interpreted differently
by different compilation schemes.  Previously working Verilog-2001 
concatentations could be re(mis)-interpreted as a struct expression.

Dave documented his opposition and posted to the reflector:
  http://www.eda.org/sv-bc/hm/2687.html

The group could not reach resolution and meeting was continued on
February 2, 8am PST.

From Feb 2, 8am PST.

Brad updated the proposal in the SVDB:

 http://www.eda.org/svdb/bug_view_page.php?bug_id=0000254

Brad moves to accept the proposal.
Stu Seconds.
Opposed: Dave Rich 'backward incompatibility, length of proposal vs. time available'
No Abstain.
Motion Passes.

Brad moves to adjourn meeting.
Steven seconds.
Meeting adjourned

Pending
11/30/04 Steven Close issue in BTF database equivalent to SVDB Issue 328
01/31/05 Brad   Update SVDB with changes related to 168
01/31/05 Brad   Update proposal for 357
01/31/05 Matt   Address Cliff's issue with attendance & voting.