Minutes of the April 12, 2005 SV-BC Ballot Resolution Committee Meeting 11000 Day 21641 00000 Month 44444 00000 Year 55555 aaaaa Matt Maidment - Intel aaaaa Brad Pierce - Synopsys aaaaa Karen Pieper - Synopsys aaaaa Dave Rich - Mentor Graphics -aaaa Cliff Cummings - Sunburst Design aa-aa Steven Sharp - Cadence --aaa Logie Ramachandran - Synopsys aaaa- Mark Hartoog - Synopsys aaaaa Gord Vreugdenhil - Mentor Graphics aaaa- Francoise Martinolle- Cadence aa-a- Kathy McKinley - Cadence aa-a- Doug Warmke - Mentor Graphics -aaa- Surrendra Dudani - Synopsys ---a- Greg Jaxon - Synopsys ---a- Stuart Sutherland - Sutherland HDL ---a- Dennis Brophy - Mentor Graphics ----a Don Mills - LCDM Engineering ----a Dan Jacobi - Intel ----a Rishiyur Nikhil - Bluespec ----- Tom Fitzpatrick - Mentor Graphics ----- Jonathan Bradford - Micronas Agenda +Review IEEE patent policy http://standards.ieee.org/board/pat/pat-slideset.ppt Reviewed. +Review Previous Meeting Minutes http://www.eda.org/sv-bc/minutes/sv-bc_05_04_11.txt Brad Moves to accept. Gord seconds. No opposed. No abstain. Motion passes. +Issue Resolution Issue 35 Steven moves to a 4/11 Gord seconds No opposed. Abstain: Mark (Not backward compatible with SV 3.1a) Karen (came in too late to discussion) Motion passes. AI: Brad put 578 in html STU1 - simulation initialization always_comb works well always @(*) more problematic Not possible to fully define time 0 behavior at this point in the process. always_comb, always_latch, combinational UDPs and gate primitives Gord moves to accept wording Change: "In Verilog, an initialization value specified as part of the declaration is executed as if the assignment were made from an initial block, after simulation has started. Therefore, the initialization can cause an event on that variable at simulation time zero. In SystemVerilog, setting the initial value of a static variable as part of the variable declaration (including static class members) shall occur before any initial or always blocks are started, and so does not generate an event. If an event is needed, an initial block should be used to assign the initial values." To: "In Verilog, an initialization value specified as part of the declaration is executed as if the assignment were made from an initial block, after simulation has started. In SystemVerilog, setting the initial value of a static variable as part of the variable declaration (including static class members) shall occur before any initial or always blocks are started." Brad seconds No opposed. No abstain. Motion passes. AI: Brad to enter proposal for STU1 in html & Mantis for Stu. Brad moves that the following be sent to 1364 in response to STU1. "Combinational constructs including continuous assignments and combinational primitives shall execute at least once during time 0." Gord seconds. No opposed. No abstain. Motion passes. AI: Matt enter this in SVDB under V-1364 Message to be included in xls file: The fundamental concerns raised by this issue are more appropriately addressed by the 1364. This committee has forwarded a specific recommendation to 1364 addressing a subset of the issue. Issue 226 was discussed. Gord expressed concerns with this proposal and bi-direction connections, valid in context of refs and the directionality of type flow (left-to-right). Gord was asked to details concerns in an email to the reflector. Next Meeting: Thursday, April 14, 7:30am-9:00am PDT Action Items Completed 04/11/05 Matt communicate result of 229 to SV-EC 04/11/05 Matt move 632 to resolved and add note that identifies it as forwarded to the EC Pending 04/01/05 Brad to propose solution to issue 91 at the April 4th meeting 04/04/05 Stu make a specific proposal for Issue 265 no later than April 13 04/11/05 Matt make proposal for 216 04/11/05 Brad transfer proposal in SVDB 336 to html for Stu 04/11/05 Steven make alternate proposal for issue 35