SV-BC Errata Committee Meeting Date: Monday, April 24, 2006 Time: 09:00am-11:00am PDT 21210000 Day 40736957 00000011 Month 44332121 00000000 Year 66666655 a-aaaaaa Matt Maidment - Intel aaaaaaaa Brad Pierce - Synopsys aaaaaaaa Shalom Bresticker - Intel --aaaaaa Cliff Cummings - Sunburst Design aaa-a-aa Surrendra Dudani - Synopsys aaaaaaaa Mark Hartoog - Synopsys ----aaaa Dan Jacobi - Intel aaaaaa-a Francoise Martinolle - Cadence aaaaaaaa Karen Pieper - Synopsys aaaaaaaa Dave Rich - Mentor Graphics aaaa-aaa Steven Sharp - Cadence a-aaaaaa Gordon Vreugdenhil - Mentor Graphics aaaaaaaa Doug Warmke - Mentor Graphics --a--aa- Don Mills - LCDM Engineering --aaaaa- Stu Sutherland - Sutherland HDL ------a- Bill Paulsen - Cadence ----a-a- Rishiyur Nikhil - Bluespec ----aa-- Chris Spear - Synopsys --a-aa-- Logie Ramachandran - Synopsys Agenda + Review IEEE patent policy http://standards.ieee.org/board/pat/pat-slideset.ppt Reviewed. + Review Minutes of Previous Meeting http://www.eda.org/sv-bc/minutes/sv-bc_06_04_10.txt Brad moves to accept minutes. Doug seconds. No opposed. Abstain: Gord (not present) + Issue Review Process: Identify subset of issues to focus committee effort Assign owners for the issues Owners bring issues to vote when draft of proposal complete Rebuttal to issues should come in the form of specific changes to proposal Guidelines for issues: - Group would prefer not to address issues that complicate merging of the LRMs or require edits to both specs. Group would prefer to address more isolated errata until next PAR is set. - Try to clarify intent of some issues even if no formal resolution. This would be useful for keeping implementations consistent. - Major Severity will be used to identify issues that if not addressed will lead to visibly different implementations - Group will use severity to quantify impact of change. Issues will be addressed in order of severity. - Priority will indicate issue's development progress. Increase in priority indicates increased progress to proposal and vote. 'Immediate' priority indicates issue is ready for a vote. - Individuals will indicate ownership of resolution by adding themselves to the 'assigned to' field. Karen will help anyone who cannot update an issue. - Individual members can increase the severity of an issue but the group must agree to decrease severity. - Status Filed: Assigned, Resolved & Closed are key states. Some initial issue groups were identified: Namespaces Issues: 30, 1213, 1214, 1220 Primary Owner: Francoise Participants: Gord, Francoise, Mark, cc: Shalom, cc: Karen I/O Errata/Clarification Issues: 672, 1078, 1386: Steven ; 988: Gord Primary Owner: Steven Participants: Steven, Gord, Mark, Francoise Enumerated Types Issues: 916, 917, 1429 Primary Owner: Matt Configurations: Issues: 986 (see bugnote for related items) Primary Owner: TBD (proposed as Cliff but he was not present) Scheduling: Issues: 1290, 219 Primary Owner: TBD (Gord; after first round of issues are addressed) AI: Matt identify any other threads of major issues Actionable Items: Per Surrendra (http://www.eda.org/sv-bc/hm/4376.html) 1051 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001051) Recommend to close the issue as it has been discussed and considered previously - " intermediate variables with @* " Steven moves to resolve as previously considered and rejected. Gord seconds. No opposed. No abstain. Motion passes. Per Gord (http://www.eda.org/sv-bc/hm/4377.html) 1176 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001176) (enhancement), feature, immediate Issue: Proposal for Extending Verilog Data Types Comment: I think this should be closed as addressed by P1800 and any remaining enhancements be filed as a new request. Gord moves to resolve as largely addressed by P1800. Remaining items should be filed separately. Steven seconds. No opposed. No abstain. Motion passes. 1174 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001174): Steven moves to resolve as covered by P1800. Brad seconds. No opposed. No abstain. Motion passes. 1179 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001179) (enhancement), text, low Issue: Add Quick Reference Comment: I'm not sure this belongs in an LRM. Dave moves to resolve at outside the scope of the PAR. Brad seconds. Opposed: Shalom (Doesn't agree that it is outside the scope of the LRM. For the same reasons that we write redundant BNFs and add explanatory text which does not add any functionality to the standard, i.e., to make it easier for the reader. Thinks readers would be very appreciative of it, especially since SV is much larger than Verilog.) No abstain. Motion Passes. 1271 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001271) (clarification), trivial, immediate Issue: A.6.2: delay_or_event_control should be optional in blocking_assignment Comment: The suggested grammar change is not strictly necessary (and in fact would create reduce/reduce conflicts if directly implemented) but does avoid an easy to make error in reading the grammar. I think that we should have an email vote on it and if anyone opposes the change, just close the issue as "won't fix" Brad moves to resolve as not a bug. Gord seconds. No opposed. No abstain. Motion passes. 1272 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001272) trivial, immediate Issue: Syntax 10-3: &&& should be all red Comment: This is a duplicate of 929. 1272 should be closed and 929 should be an email vote. Brad moves to resolve as a duplicate of 929 Gord seconds. No opposed. No abstain. Motion passes. 929 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0000929) Brad moves to accept proposal. Gord seconds. No opposed. No abstain. Motion passes. Actionable Items for future meetings: 1291 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001291) feature, immediate Issue: range and signedness are parallel attributes of every packed dimension Comment: Brad has suggested that we close this as "won't fix". I agree. Per Karen (http://www.eda.org/sv-bc/hm/4378.html) 1127 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001127) Close Add shared declaration mechanism to Verilog - packages Per Shalom (http://www.eda.org/sv-bc/hm/4385.html) 1125 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001125) I added a proposal to close 1125 as implemented in 1364-2005. 1128 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001128) I added a proposal to close 1128 as implemented in 1800-2005. 1135 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001135) 1135 has a proposal to reject and close the issue. Per Doug 1319 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001319) 1194 (http://www.eda.org/svdb/bug_view_page.php?bug_id=0001194) + Next Meeting Date: May 8th Action Items Completed Pending 01/09/2006 Matt assemble issue list for future work 01/09/2006 Matt find owners for future work issues 03/13/2006 Matt Open up SV-BC Issue requesting an index for P1800 03/27/2006 Matt add SVDB 980 to agenda when final draft of 1364-2005 is released 03/27/2006 Cliff post examples demonstrating the need for 0-1 wildcard to justify further action on SVDB 99 04/10/2006 Steven to create proposal for SVDB 1386 04/10/2006 Steven to create proposal for SVDB 1078 04/10/2006 Gord requested to create proposal for SVDB 988 04/24/2006 Matt identify any other threads of major issues