SV-BC Meeting Date: Monday, September 13, 2010 Time: 9:00am-11:00am PDT Toll Free Dial In Number in North America: 1-888-813-5316 Caller Paid Dial In Number: 1-650-584-6338 Meeting ID: 7839818 13101 Day 30629 00000 Month 98887 11111 Year 00000 aaa-a Matt Maidment - Intel a-aaa Brad Pierce - Synopsys aaaaa Mark Hartoog - Synopsys aa-aa Dave Rich - Mentor Graphics aaaaa Gordon Vreugdenhil - Mentor Graphics -aa-a Alex Gran - Mentor Graphics a--aa Heath Chambers - Consultant/Trainer aaa-a Tom Alsop - Intel aaaaa Cliff Cummings - Sunburst Design aaaaa Shalom Bresticker - Intel --aaa Don Mills - LCDM Engineering aaaaa Arnab Saha - Mentor Graphics aa-aa Daniel Schostak - ARM a--aa Kaiming Ho - Fraunhofer Institute aaaa- Steven Sharp - Cadence aaaaa Francoise Martinolle - Cadence aa-aa Eric Coffin - Mentor Graphics ----- David Gates - AMD aa--a Peter Flake - Elda Technology ----- Scott Little - Freescale ----- John Havlicek - Freescale ----- Rishiyur Nikhil - BlueSpec a---a Jonathan Bromley - Verilab ---a- Greg Jaxon - Synopsys a---- Linc Jepson - 74ze Agenda + Review IEEE patent policy http://standards.ieee.org/board/pat/pat-slideset.ppt Reviewed. + Previous Meeting Minutes http://www.eda.org/sv-bc/minutes/sv-bc_10_08_30.txt Gord Cliff No opposed: None Abstain: Heath, Kaiming, Brad, Jonathan (Did not attend meeting). Motion passed. + Continue Interface Discussion Based on feedback from the last meeting, Peter Flake posted additional comments: http://www.eda.org/sv-bc/hm/10530.html Gord asserts Peter's concepts are reasonable for the design side, but is concerned about the testbench side. There's already a challenge to determine compatibility between a virtual interface to an interface. Looking for a more strongly typed specification for interacting with an interface. Exporting/importing sub-programs would be cumbersome with interfaces within interfaces. In practice, seeing interfaces primarily for connecting TB to design using a virtual interface. Perhaps there are other ways for improving connecting between design and testbench. Dave suggests pursuing two directions: fixing interfaces for design and improving testbench connection to design. Mark sees more aggressive use of SystemVerilog for the testbench and suggests prioritizing connection between testbench and design. Others suggest identifying key issues and addressing those (parameterization, timing). Another possibility is to find a way to publish a methodology paper to guide users or explore ideas of subinterfaces and class-based design connection. Kaiming's issue of lack of arrayed interfaces sounds like a valid issue for the design side. Suggestion was made for SV-BC to communicate that it will not address issues of connecting testbench to the design and that BC not pursue further work on interfaces. Question was raised bout number of design-related issues. Mantis 2318 is master interface issue. Quick review identified design-related issues. Believe design and testbench issues can be separated. AI: Shalom to review 2318 and classifying issues as testbench or design. AI: Jonathan show simple examples of virtual interfaces, sub-interfaces and base classes in modules to demonstrate different methods for connecting design and testbenches. Dave Rich agrees this would productive. Mark raised that there are issues using interfaces with configurations. How is an interface name port bound if you have multiple libraries and interfaces of the same name in different libraries? No way to specify a port in a configuration. This is Mantis 3048. Mark believes this be addressed. 10:57AM: Steven moves to adjourn. + Progress/Discussion for Top 10 Looking for proposal sketches or discussion for any of these issues. 696 - Champion: Tom 2310(1084, 1201) - Participants: Eric, Tom, Shalom, Steven, Wilson Snyder 3053 - Participants: Francoise, Mark, Alex, Kaiming 3055 - Participants: Gord, Mark 2991 - Champion: Tom, Participants: Steven 1566 - For future discussion 2114 - Similar to 3053. Have same group look at it. 210 - Participants: Shalom, Matt 3056 - Champion: Shalom, Participants: Steven, Francoise Action Items Outstanding 05/10/10 Matt create Master Issue for WG-approved SV-BC Top-25 07/19/10 Matt follow-up about voting rules for technical sub-committee. Is there a limit on the number of reps from 1 entity? 07/19/10 Dave to post request to reflectors for clarification of 2108 07/19/10 Jonathan post some items for discussion related to 2114 to reflector. 08/02/10 Brad give SV-BC feedback on Mantis 2992 to Mehdi 08/02/10 Eric start reflector thread on Mantis 2310 08/02/10 Gord meet F2F with Mark when in Bay Area 08/16/10 Tom write up class static method examples and explanation for inclusion in clause 8 and reference in clause 13 and 3.8. 08/16/10 Brad update Mantis items passed by email vote. 08/16/10 Matt to rethink 210 in terms of configuration and alias. 08/16/10 All send Shalom feedback about prioritizing the issues raised in port declaration issue summary: http://www.eda.org/sv-bc/hm/10498.html 09/13/10 Shalom review 2318 and classifying issues as testbench or design 09/13/10 Jonathan show simple examples of virtual interfaces, sub-interfaces and base classes in modules to demonstrate different methods for connecting design and testbenches.