SV-BC Meeting Date: Monday, March 28, 2011 Time: 9:00am-11:00am PDT Toll Free Dial In Number in North America: 1-888-813-5316 Caller Paid Dial In Number: 1-650-584-6338 Meeting ID: 7839818 211310202213101 Day 844176285730629 000001111000000 Month 332112110998887 111111111111111 Year 111110000000000 a-aa-a-a-aaaaa- Steven Sharp - Cadence aaa-aaaaa-aaaaa Francoise Martinolle - Cadence a-aaaaaaaaa--aa Kaiming Ho - Fraunhofer Institute aaaaaaaaaaaaa-a Matt Maidment - Intel aa-aaaaaaaaaa-a Tom Alsop - Intel aaa-aaaaaaaaaaa Shalom Bresticker - Intel aaaaaaaaaaaa-aa Dave Rich - Mentor Graphics aaaaaa-aaaaaaaa Gordon Vreugdenhil - Mentor Graphics a-aa-aaaaa-aa-a Alex Gran - Mentor Graphics aaaaaaa-aaaaaaa Arnab Saha - Mentor Graphics -a-aaa-aa-aa-aa Eric Coffin - Mentor Graphics aaaaaaaaaaa-aaa Brad Pierce - Synopsys aaaaaaaaaaaaaaa Mark Hartoog - Synopsys ----a--------a- Greg Jaxon - Synopsys --------------- Scott Little - Freescale --------------- John Havlicek - Freescale --aa------aaaaa Cliff Cummings - Sunburst Design --aa-aaa--a--aa Heath Chambers - Consultant/Trainer --aaaa-aa---aaa Don Mills - LCDM Engineering --a-a---a-aa-aa Daniel Schostak - ARM --aa-a--------- David Gates - AMD --aaaa-a-aaa--a Peter Flake - Elda Technology ---aa-aaaaa---- Linc Jepson - 74ze --------------- Rishiyur Nikhil - BlueSpec ----------a---a Jonathan Bromley - Verilab Agenda + Review IEEE patent policy http://standards.ieee.org/board/pat/pat-slideset.ppt Mark moves to consider it reviewed. Gord seconds. No opposed. No abstain. Motion passes. + Review previous meeting minutes http://www.eda.org/sv-bc/minutes/sv-bc_11_03_14.txt Gord moves to approve the minutes. Mark seconds. No opposed. Abstain: Alex (not in attendance) Motion passes. + Any input on constant expression issues related to 3055? There was considerable traffic on the reflector related to these issues that led to some focus on the issue of hierarchical names in instance overrides. http://www.eda.org/sv-bc/hm/10934.html Brad asked about the history of permitting this. Steven says that it has been in Verilog-XL but was unsure if it was intentionally or unintentionally permitted. Mark would like to forbid hierarchical expressions in parameter instance overrides to make the rules consistent. Brad tried to forbid it during 1364 but could not. Implementations now allowing various flavors of support for this. Defining simple rules would break backward compatibility. Codifying all rules supported today would be challenging as they are embedded in implementations. Options: Make it illegal, leave it as legacy or complete defintion of features and extend consistency to all related features. Many assert that making it illegal is simplest path to defining the behavior but because it was already permitted it will not allow implementations to enforce the new rule. For a defparam can target downward reference through a generate. Illegal case for defparam reference is upward across a generate. Gord's proposal: When have a hierarchical reference to a parameter, that reference should be upwards or if downward, cannot cross a generate scope. Mark asked about class parameter overrides. Steven asked about what the BNF supports. Response is that it is the same as modules. Interfaces in the same state due to reusing same BNF. Gord uncomfortable shutting this down for classes as it forbids references into interfaces and it is a useful feature. Would rather extend proposed module parameter limitation here. Matt asked for specific rules that can either be aligned with this rule or denied based on limitations. 2856: Brad asked why not make this legal? Gord raised the point to hierarchical references to variables different than parameters. The topological shape of the design involves scopes and parameters but the nature of variables does not participate in the structure of the design. Concerned about opening up this possibility. To improve the specification need to agree on what is known when an expression is evaluated during elaboration. Querying variables has complicated expectations. AI: Matt for April 11, 2011 meeting add 2856 and follow-up on Gord's proposal to limit hierarchical references for parameters in module instantiations. 10:58AM Gord moves to adjourn. + Examples for Issue 210 No time. Top 25 Mantis Items 696 - Complete 2310(1084, 1201) - Participants: Eric, Tom, Shalom, Steven, Wilson Snyder 3053 - Participants: Francoise, Mark, Alex, Kaiming 3055 - Participants: Gord, Mark 2991 - Champion: Tom, Participants: Steven 1566 - For future discussion 2114 - Similar to 3053. Have same group look at it. 210 - Participants: Shalom, Matt 3056 - Champion: Shalom, Participants: Steven, Francoise 1084 - Logical Expressions in Macros 2115 - X-Optimism/X-Pessimism resolution 3073 - Collected $bits issues 1697 - Macro Loops 1202 - Define Standard Preprocessor 1251 - X/Z behavior in various contexts 2289 - parameters inside comp unit & gen block are local 1504 - parameterized structs and unions 1144 - Out-of-bound array address 2081 - always_comb statements 1553 - nested module clarifications 2684 - variable part-selects 1861 - major modport enhancements 1523 - behavior of ?: on complex types 3074 - Connectivity Enhancements 2124 - `default_nettype var-type directive Action Items Complete 02/14/11 Matt update 2991 on status and link to Mantis covering AOP and notify SV-EC. Outstanding 05/10/10 Matt create Master Issue for WG-approved SV-BC Top-25 07/19/10 Matt follow-up about voting rules for technical sub-committee. Is there a limit on the number of reps from 1 entity? 07/19/10 Dave to post request to reflectors for clarification of 2108 07/19/10 Jonathan post some items for discussion related to 2114 to reflector. 08/02/10 Brad give SV-BC feedback on Mantis 2992 to Mehdi 08/02/10 Eric start reflector thread on Mantis 2310 08/02/10 Gord meet F2F with Mark when in Bay Area 08/16/10 Matt to rethink 210 in terms of configuration and alias. 08/16/20 All send Shalom feedback about prioritizing the issues raised in port declaration issue summary: http://www.eda.org/sv-bc/hm/10498.html 09/13/10 Jonathan show simple examples of virtual interfaces, sub-interfaces and base classes in modules to demonstrate different methods for connecting design and testbenches. 09/27/10 Review Shalom's list of interface issues and suggest issues to tackle now. 05/10/10 Matt create Master Issue for WG-approved SV-BC Top-25 07/19/10 Matt follow-up about voting rules for technical sub-committee. Is there a limit on the number of reps from 1 entity? 07/19/10 Dave to post request to reflectors for clarification of 2108 07/19/10 Jonathan post some items for discussion related to 2114 to reflector. 08/02/10 Brad give SV-BC feedback on Mantis 2992 to Mehdi 08/02/10 Eric start reflector thread on Mantis 2310 08/16/20 All send Shalom feedback about prioritizing the issues raised in port declaration issue summary: http://www.eda.org/sv-bc/hm/10498.html 09/13/10 Jonathan show simple examples of virtual interfaces, sub-interfaces and base classes in modules to demonstrate different methods for connecting design and testbenches. 09/27/10 Review Shalom's list of interface issues and suggest issues to tackle now. 11/22/10 Brad to file Mantis item for upward passing of interfaces. 12/06/10 Matt open new Mantis item covering determination of port kind for .named_port connection (23.2.2.3). 01/31/11 All check with users regarding viability of rule that virtual interface declarations require that the referenced interface be previously parsed. 02/14/11 Users consider proposed restrictions and use-cases for varargs and provide feedback. 03/14/11 Matt talk to Karen about Accellera plans for participation. Questions about how to get user input, especially for bugs. 03/14/11 Matt check back with Gord and Mark in April about feedback regarding interface issues. 03/14/11 All drill down on 3055 and identify issues that would be straightforward to clarify regarding constant expressions, type operations and what is a hierarchical name. 03/14/11 Matt code examples for 210 and make proposal to resolve. 03/28/11 Matt for April 11, 2011 meeting add 2856 and follow-up on Gord's proposal to limit hierarchical references for parameters in module instantiations.