Subject: [Fwd: Minutes of sv-cc meeting, 7/23/2002]
From: Yatin Trivedi (trivedi@pacbell.net)
Date: Mon Aug 05 2002 - 21:37:39 PDT
Just a quick reminder for tomorrow's call.
Primary topics for agenda tomorrow:
- Review and approve minutes of last meeting
- Address any procedural issues
- Review outcome of assigned action items from last meeting
- Discuss Requirements document sent by Andrzej
- Any other items
Please plan to join promptly at 12:00 pm Eastern, 9:00 am pacific.
Looking forward to a lively 1 hour call.
Regards
Yatin
Joao Geada wrote:
>
> ***************************************************************
> Next Meeting: Tuesday 8/6 at 12:00 noon east coast time
> Meetings Schedule and Call Info:
> PARTICIPANT INFORMATION:
> -----------------------
>
> All Participants should use the following information to reach the
> conference call:
> * PARTICIPANT CODE: 707131
> * Toll Free Dial In Number: (877)807-5706
> * International Access/Caller Paid Dial In Number: (225)383-8961
> SV-CC (07/23/2002)
> ****************************************************************
>
> Minutes of last meeting 7/23
>
> Attendees:
> [xx] Ghassan Khoory (Synopsys, Co-Chair)
> [xx] Kevin Cameron (NSC)
> [xx] Simon Davidmann (Co-Design)
> [xx] Peter Flake (Co-Design)
> [xx] Joao Geada (Synopsys)
> [x-] Tayung Liu (Novas)
> [xx] Andrzej Litwiniuk (Synopsys)
> [x-] Mike McNamara (Verisity)
> [xx] Stuart Swan (Cadence)
> [-x] Bassam Tabbara (Novas)
>
> Minutes:
> ========================================
>
> Meeting started 10minutes late. We all agreed that all following
> meetings will start on time. We will not wait for latecomers to start
> the meetings.
> Joao assigned task of taking minutes.
>
> Stuart reopened discussion on the goals of this sub-committee, as we
> did not have a voted agreement on this subject last meeting. After
> discussion we all voted and unanimously agreed on the following:
>
> 1- this sub-committee cannot deliver enhancements to PLI/VPI to cater
> for the enhancements and/or changes to Verilog introduced by
> SystemVerilog on the time-frame given, for the following reasons:
>
> a) time constraints: the task is considerable, touching on all
> facets of the enhancements/modifications introduced by
> SystemVerilog.
>
> b) dependencies: the task can be achieved only once the language
> stabilizes. As this is being performed by different
> sub-committees, there is an inter-comittee dependency.
>
> 2- this sub-commitee will defer any work related to PLI/VPI
> definition. We consider that this task is more appropriately
> handled by each and every group that is modifying the language; if
> assigned to us, the issues raised in point 1) need to be addressed.
>
> 3- with the presumption that VPI will be reassigned/deferred, this
> committee believes its first priority/task consists of defining the
> direct foreign language interface (directC like interface) to
> SystemVerilog.
>
> All attendees voted, all in agreement.
>
> NOTES: (led by Peter)
>
> The above does not mean to imply that we do not believe VPI/PLI to
> be important. We do not believe that SystemVerilog can be considered
> complete without defining the necessary extensions to
> PLI/VPI. However, due to the aforementioned issues, we do not
> believe we are the appropriate committee to tackle such a
> definition.
>
> ACTION ITEM: Ghassan: to communicate the above agreement to the primary
> SystemVerilog committee and/or Vassilius (as appropriate). We need to
> ensure that group as a whole understands what this committee will be
> doing and to ensure that VPI/PLI definition will not be dropped. We
> also need confirmation that the agreement we've reached is acceptable
> to the primary committee.
>
> Then we discussed the process by which we will defined the direct
> foreign language interface. Following Stuart's recommendation, we will
> first agree on the requirements that this interface has to satisfy.
>
> ACTION ITEMS:
> Andrzej: send to reflector the Synopsys understanding of requirements
> Peter: send to reflector the CoDesign understanding of requirements
> [action items assigned to companies that already possess a similar
> interface, drawing from their experience and the requirements that led
> them to develop such interfaces in the first place]
>
> Joao
> ==============================================================================
> Joao Geada, PhD Sr. Staff R&D Engineer Verif Tech Group
> Synopsys, Inc TEL: (508) 263-8083
> 154 Crane Meadow Road, Suite 300, FAX: (508) 263-8069
> Marlboro, MA 01752, USA
> ==============================================================================
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