Subject: My vote for the directC donation
From: Francoise Martinolle (fm@cadence.com)
Date: Fri Sep 27 2002 - 15:07:04 PDT
Yatin and all,
Despite I very well recognize that there are strong market requirements to
ease
the combined use and inter-communication of Verilog and C/C++,
and I recognize that the DirectC interface is an attempt to accomplish this,
I need to vote NO towards taking the donation as the basis of our work
towards defining
a better C/C++ systemVerilog integration for the following reasons:
1. DirectC interface creates user-defined system tasks and functions
which only have read and write access to its parameters.
This can be accomplished many other ways without defining a new
interface.
In fact verilog simulators have already implemented
optimizations by recognizing
such tasks and functions.
2. Abstract versus Direct access
The abstract access seems to be a remedy for the difficulty of
using the direct mode.
Asking the user to use a 2 steps methodology for safety-sake is
cumbersome
and non user-friendly.
The VPI creation of handles has exactly the same goal and
effect as the abstract mode.
3. Data types:
The DirectC interface does not deal with the systemVerilog
Data types.
SystemVerilog does not have a pointer type which is a very
powerful
type to the C language
4. Limitations on building an heterogeneous system using Verilog and C or C++:
a) limitation on Verilog/C modules hierarchy: there is no
possibility to build
any hybrid Verilog/C design hierarchy.
b) You cannot instantiate Verilog from the C module, neither
can you call Verilog
tasks and functions from the C module.
c) Cmodules are black boxes for the rest of the design
d) Cmodules have only a few hardware constructs: concurrency
and delay
Francoise
'
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