Subject: Re: ISSUE:DirectC:DirectC i/f should support mechanism for calling Verilog task/function from a DirectC application
From: Swapnajit Mittra (mittra@juno.com)
Date: Wed Oct 23 2002 - 01:13:40 PDT
On Mon, 21 Oct 2002 17:30:56 -0700 "Warmke, Doug"
<doug_warmke@mentorg.com> writes:
Swapnajit,
Some brief comments on your proposal.
We can discuss more at the appropriate time in the meeting or in email.
>
> o If an external C function calls a Verilog task, no
> simulation time must elapse during the execution of that task.
> (This is, because a C function in DirectC is a zero-time event).
> However, no such restriction shall be in place when a Verilog
> task is called from a cmodule.
>
I think this is overly restrictive. It will not work out well if
some implementations want to directly integrate C models
living in a threaded environment (e.g. TestBuilder, SystemC)
together with HDL models. Let's keep an open mind
about making large scale changes to DirectC.
Doug,
I understand your concern. But, can not these C models
be written as cmodules (or be embedded within cmodules) ?
I think (Joao, correct me if I am wrong) a DirectC
external C function and a cmodule to some sense
are analogous to a Verilog function and task respectively.
External C functions are 0-time activities whereas
cmodules are not.
I would not mind if we change that proposition (that DirectC
external C functions should be 0-time activity), but my
concerns there are:
o Whether that will break any other basic structure of the
whole scheme.
o Whether we have sufficient time to undertake this type of
fundamental changes. Personally I think we should rather be
late than producing things that are half cooked, but I know
we are working under some tight schedule here.
-- Swapnajit Mittra Project VeriPage ::: http://www.angelfire.com/ca/verilog________________________________________________________________ Sign Up for Juno Platinum Internet Access Today Only $9.95 per month! Visit www.juno.com
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