Subject: Re: Patent Disclosure relating to Testbench Automation and Covera ge
From: Yatin Trivedi (trivedi@pacbell.net)
Date: Fri Oct 25 2002 - 07:36:02 PDT
Vassilios,
Thank yo ufor clarification and Accellera's position.
Regards
Yatin
Vassilios.Gerousis@Infineon.Com wrote:
> Dear members of CC,
> I thank Michael McNamara for disclosing the patent on this topic.
> This patent disclosure is now an Accellera board business and it should not
> affect the process that we have started in this committee.
>
> The committee should continue the discussion and also the voting
> that has started by the chair. On a technical basis, we will examine the
> patent(s) that Verisity has disclosed and see if (it) they pertain to the
> syntax or semantic of the API. If it pertains to implementation of an
> algorithm, then it is does not pertain to the topic at hand. If it pertains
> to Syntax or Semantics we can change what we have so that we do not conflict
> with the patents.
>
> We had a similar situation on Verilog-A where Cadence failed to
> disclose a patent on the syntax at the beginning of standard development.
> They disclosed the matter near the end of the standardization process. At
> that time we had the option to develop new syntax and/or negotiate a free
> license on the patent. The board decided to work with a free license on
> Verilog-A.
>
> In summary, please do not let such an email affect your voting
> confidence. The voting process will continue. We will also continue our
> technical discussions on the donations. We will report more on this topic,
> as more materials is made accessible to us by Verisity.
>
> Best Regards
>
> Vassilios Gerousis
>
> -----Original Message-----
> From: Michael McNamara [mailto:mac@verisity.com]
> Sent: Friday, October 25, 2002 12:37 AM
> To: System Verilog CC Committee
> Cc: Lynn.Horobin@verisity.com; Accellera Secretary
> Subject: Patent Disclosure relating to Testbench Automation and Coverage
>
>
>
> Hello Committee Members,
>
> In the spirit of full disclosure, we want to disclose that Verisity
> Design, Inc. has been granted a patent in the field of Testbench
> Automation and Coverage: U.S. Patent 6,141,630 entitled "System and
> Method for Automated Design Verification".
>
> This patent, and additional patent protections on similar subject
> matter, may apply to topics being discussed by this Committee,
> including the current donation.
>
> We are making this disclosure to ensure that the Committee is aware
> of all patent claims that Verisity has obtained or is pursuing and
> that are relevant to the Committee's work.
>
> Regards, Michael McNamara
> Sr. VP Verisity Design
>
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