Subject: Re: [sv-cc] more about import/export
From: Stickley, John (john_stickley@mentorg.com)
Date: Fri Mar 07 2003 - 07:12:31 PST
Doug,
We're in agreement.
Just a quick not to add about scope vs. context.
Warmke, Doug wrote:
> >
> > johnS:
> > The thing I don't like about the term "scope" is scope pertains to
> > "module scope" whereas context pertains to "module instance".
> >
> > The two are very different and we want our term to denote the latter.
> >
> > Let me embellish:
> >
> > module foo;
> > module bar;
> > integer a;
> > endmodule
> > endmodule
> >
> > module top
> > foo x();
> > foo y();
> > endmodule
> >
> > Scope of integer a:
> > foo::bar::a
> >
> > Instances of module a:
> > top.x.bar.a
> > top.y.bar.a
> >
> > In this case integer a has only 1 possible scope but
> > 2 possible contexts. That's why I would prefer to
> > keep the term "context" since instance path is truely
> > what we want. If we want to change terms, "instance"
> > would be more appropriate than "scope" but I would just
> > as soon keep "context".
>
> DOUG: This is just a definition of terms.
> In Verilog, the term "scope" does refer to module instance,
> not module definition. Consider the Verilog-XL $scope
> interactive command, which changes the current module instance.
> Or the VCD file format, with its $scope and $upscope keywords
> that denot current module instance. "scope" means what you
> want it to mean in Verilog-talk.
johnS:
After looking over the 1364 LRM I realized you're right here.
I'm thinking of it from the point of view if VHDL where
scope very explicitly has the meaning I described. I think this
purer meaning is more universal among general programming languages
but then, we've seen Verilog buck that trend before haven't we ?
So, if that's the case, is there a Verilog term for scope
as I had defined it ? What is it ?
VHDL Verilog
---- -------
instance path scope
scope ????
Perhaps a term for the other meaning of scope was never
coined in Verilog because until SystemVerilog, nested module
scopes where never a language feature ? VHDL has always
had 'block' statements and near as I can tell, nested modules
are SystemVerilog's answer to VHDL blocks.
-- johnS
__
______ | \
______________________/ \__ / \
\ H Dome ___/ |
John Stickley E | a __ ___/ / \____
Principal Engineer l | l | \ /
Verification Solutions Group | f | \/ ____
Mentor Graphics Corp. - MED C \ -- / /
17 E. Cedar Place a \ __/ / /
Ramsey, NJ 07446 p | / ___/
| / /
mailto:John_Stickley@mentor.com \ /
Phone: (201)818-2585 \ /
---------
This archive was generated by hypermail 2b28 : Fri Mar 07 2003 - 07:17:26 PST