Subject: [sv-cc] Mail from ["Clifford E. Cummings"
FYI.
---------- Forwarded Message ----------
Date: Tue, 05 Aug 2003 11:06:25 -0700
To: sv-cc@server.eda.org
From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
Subject: Request: Call time-consuming Verilog tasks from C
Hello SV-CC Committee -
I tried to do a search on this topic from the sv-cc email repository and it
looks like the subject was somewhat addressed last October, but I am not sure.
Superlog had the ability to call Verilog tasks from C - a rather nice
feature that is not currently in SystemVerilog.
I could have a posclk task that waited for a posedge clk, and call it from
C. Now I could have multiple clocks and still schedule C-events with
respect to the different clocks. This was already implemented in a vendor
tool (a key requirement for new SV 3.1a proposals), and this capability
meant I did not have to use SystemC to consume time in a simulation. I
could use plain old C.
This was a key selling point for Superlog. I was quite disappointed to find
that SystemVerilog could not do this. As a user, I would like to see this
capability donated from Synopsys (Co-Design-Superlog) and added to
SystemVerilog.
Regards - Cliff Cummings
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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This archive was generated by hypermail 2b28
: Tue Aug 05 2003 - 15:37:53 PDT
From: Swapnajit Mittra (mittra@juno.com)
Date: Tue Aug 05 2003 - 15:35:37 PDT
--
Swapnajit Mittra
Project VeriPage ::: http://www.angelfire.com/ca/verilog