Subject: [sv-cc] Separate Compilation Proposal for review
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Oct 31 2003 - 14:05:37 PST
Karen asked me to forward this to sv-ec and sv-cc since she is not either of
these reflectors.
Regards
David
-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Karen
Pieper
Sent: Friday, October 31, 2003 1:37 PM
To: sv-bc@eda.org
Subject: [sv-bc] Separate Compilation Proposal for review
Dear committee members,
The Separate Compilation working group of the SV-BC has completed their
work on a recommendation to enhance SystemVerilog to support separate
compilation. The proposal that was approved by the working group is
available. ( http://www.eda.org/sv-ec/hm/att-1461/01-Packages_Sep_V5.pdf ).
This proposal was discussed at the last SV Chairs meeting where the
decision was made that each committee needs to be aware of the changes
being proposed, review the changes, and then provide feedback to the SV-BC.
The proposal will be reviewed, discussed, modified, and then voted on
within the SV-BC committee.
After the vote was taken within the working group there were some
discussions that suggested the proposal could be improved in order to
clarify the intent of the working group. Also available is a modified
version of
the approved proposal that includes suggested improvements
( http://www.eda.org/sv-ec/hm/att-1461/02-Packages_Sep_V8.pdf ). Please
review this document as well and provide
feedback to SV-BC.
Please have all comments or suggestions sent by next Friday (7 November) so
that the SV-BC can finish its review and vote on the document at the
upcoming Face-to-face meeting on 10 November 2003.
Thank you,
Karen Pieper
Chair, Separate Compilation Task Force
This archive was generated by hypermail 2b28 : Fri Oct 31 2003 - 14:07:07 PST