Subject: RE: [sv-cc] Today's SV VPI Update
From: Joao Geada (Joao.Geada@synopsys.com)
Date: Mon Jan 19 2004 - 15:19:11 PST
MessageBassam,
thanks for the feedback. I'll be quite busy tomorrow, but I should be able
to incorporate the changes on Wednesday.i
I'll update the vpi_user.h file on the same timeframe.
Joao
============================================================================
==
Joao Geada, PhD             Principal Engineer                Verif Tech
Group
Synopsys, Inc                                              TEL: (508)
263-8083
377 Simarano Drive, Suite 300,                             FAX: (508)
263-8069
Marlboro, MA 01752, USA
============================================================================
==
  -----Original Message-----
  From: Bassam Tabbara [mailto:bassam@novas.com]
  Sent: Monday, January 19, 2004 5:29 PM
  To: Joao.Geada@synopsys.COM
  Cc: sv-cc@eda.org
  Subject: RE: [sv-cc] Today's SV VPI Update
  Joao, [this is an html email so I can paste the fixes ...]
  My apologies for this oversight on my part, somehow I never sent the first
part out of this email earlier ... sorry about that. A couple of
enhancements remain in the property part, here's what I see (in the rev you
just sent out) to more accurately reflect draft3 (most are just additions
similar to what you have already, so not a big issue, nothing is wrong, just
need a bit more beef up ...): As far as I can tell this all I see.
  PART I: Diagrams
  1) vpiPropertyOpType needs to also have: vpiAnd,  vpiOR, and if/else , see
the following (draft3)
  property_expr ::=
  sequence_expr
  | ( property_expr )
  | not property_expr
  | property_expr or property_expr
  | property_expr and property_expr
  | sequence_expr |-> [ not ] sequence_expr property_expr
  | sequence_expr |=> [ not ] sequence_expr property_expr
  | if ( expression ) property_expr [ else property_expr ]
  | property_instance
  2) property expr needs to also have "multiclock property expr"
before/under property expr, and then a new diagram for "multiclock property
expr"  of the form (similar to property expr)
  multi_clock_property_expr ::=
  property_expr
  ! multi_clock_sequence
  | clocking_event multi_clock_property_expr
  | ( multi_clock_property_expr )
  | not multi_clock_property_expr
  | multi_clock_property_expr or multi_clock_property_expr
  | multi_clock_property_expr and multi_clock_property_expr
  | multi_clock_sequence |-> multi_clock_property_expr
  | multi_clock_sequence |=> [ not ] multi_clock_sequence
multi_clock_property_expr
  | if ( expression ) multi_clock_property_expr [ else
multi_clock_property_expr ]
  | property_instance
  3) Multi clock sequence expression also needs some enhancements (top
figure in below, needs to be more enhanced with "ops" too
  Add the following:
  multi_clock_sequence::=
  clocked_sequence { ## clocked_sequence }
  sequence_expr
  | clocking_event multi_clock_sequence
  | ( multi_clock_sequence )
  | multi_clock_sequence ## multi_clock_sequence
  PART II: vpi_user.h: missing the assertion/coverage/Read VPI... what's the
plan for this ?
  Thx.
  -Bassam.
  --
  Dr. Bassam Tabbara
  Technical Manager, R&D
  Novas Software, Inc.
  http://www.novas.com
  (408) 467-7893
  > -----Original Message-----
  > From: owner-sv-cc@server.eda.org
  > [mailto:owner-sv-cc@server.eda.org] On Behalf Of Joao Geada
  > Sent: Monday, January 19, 2004 1:04 PM
  > To: Sv-Cc
  > Cc: Tapati Basu; Avinash G Mani; Charles Dawson; Francoise Martinolle
  > Subject: [sv-cc] Today's SV VPI Update
  >
  >
  > Hi all,
  >
  > attached is the last major update that I was expecting for
  > the SV VPI extensions. This update includes some minor fixes
  > to a number of diagrams, adds the expression diagrams,
  > interface specify blocks, assignment stmts (to deal with the
  > assignment operators, section 7.3), etc
  >
  > Additionally, this version provides a the sv_vpi_user.h file
  > with the names of all the new VPI constants (though with no
  > numbers assigned to the various constants, as I expect that
  > some specific number range will be assigned for SystemVerilog)
  >
  > The only things in SystemVerilog that know are not
  > represented by these diagrams are:  section 12.6 (random
  > sequence generation)  section 20 (coverage)
  >
  > Joao
  >
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