Looks good, Michael.
I do have a question about the formatting of the coding
in F.1 in both 205 and 330.  The spacing, indentation,
etc., seems a little irregular, though technically correct.
Do we want to give Stu some specific guidance on the
formatting?
Regards,
Jim V.
--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 
] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] Behalf Of Michael Rohleder
] Sent: Wednesday, December 01, 2004 2:03 PM
] To: SystemVerilog CC DWG
] Subject: [sv-cc] Errata #63, #158, #330 amended as discussed 
] in today's meeting
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Received on Wed Dec  1 12:48:43 2004
This archive was generated by hypermail 2.1.8 : Wed Dec 01 2004 - 12:48:46 PST