RE: [sv-cc] SV-CC agenda for 12/08/2004

Charles, we should also consider #332, because the
champions are holding up V-640 (uwire) pending our
review of 332. The proposal for V-640 at

  http://boyd.com/1364_btf/report/full_pr/640.html

already contains an update to vpi_user.h. Unless
we decide we need another change, we may merely
have to rubber-stamp V-640.

Regards,
Jim V.

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James H. Vellenga 978-262-6381
Engineering Director (FAX) 978-262-6636
Cadence Design Systems, Inc. vellenga@cadence.com
270 Billerica Rd
Chelmsford, MA 01824-4179
"We all work with partial information."
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] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On
] Behalf Of Charlie Dawson
] Sent: Tuesday, December 07, 2004 6:14 PM
] To: SV-CC
] Subject: [sv-cc] SV-CC agenda for 12/08/2004
]
] Hi All,
]
] The call-in information for this meeting is as follows:
]
] U.S. 866-807-0627
] International 203-955-5179
] Passcode 399143
]
] Meeting will start at 11:30am EST (4:30pm GMT), and last for
] 1.5 hours.
]
] -Chas
]
]
] AGENDA
]
] 1. Review Patent information
]
] Go to:
] http://standards.ieee.org/board/pat/pat-slideset.ppt
]
] 2. Review minutes from last meeting (12/01/2004)
]
] 3. Liaisons
]
] - Chas/Francoise to report on Champions meeting.
] - Anyone care to make a report?
]
] 4. New business
]
] - 201 More details needed on DPI string argument handling
] - 334 null bytes in strings
] - 050 Change DPI svLogicVec32 representation to match
] PLI/VPI aval/bval representation
] - 064 Note 20 of section 31.10 is unclear
] - 333 VPI support for types on wires
] - 053 VPI access to instances and packages is incorrect
] - 054 What is the vpiFullName of a package?
] - 055 fullnames of declarations in the global scope of a
] compilation unit
] - 056 vpi_handle_by_name on imported items?
] - 062 Conflicting vpiArray property descriptions in 31.10
] - 077 VPI diagram for instances shouldn't refer to reg objects
] - Others?
]
] 5. Review SV-CC items with proposals:
]
] 6. Review SV-CC items with proposals (Straw poll only):
]
] 7. Review old business:
]
] SV-CC action items:
] - Francoise to ask Peter Ashenden what was done to improve
] printing from Rational Rose.
] - Francoise to inquire about the feasibility of third parties
] shipping the UML for the diagrams.
] - Bassam to update 265 as amended.
] - Michael to update 158 as amended.
] - Sachi to drive finding a better solution for 052.
] - Chas to add colors to proposals for 310 and 040.
] - Chas to add Stu to SV-CC email alias.
]
] PTF action items:
] - Steve to compare BNF with the access available
] for attributes to see if they match
] - Francoise to remove "+" from tags in UML diagrams and
] add vpi prefix where appropriate.
] - Francoise to send out HTML for 1364-2001 diagrams, using
] something other than JPG for importing diagrams into frame.
] - Stu to write proposal for PTF 368.
] - Francoise to write proposals for PTF 373, 374, and 396.
] - Steve to write proposals for PTF 311, and 495.
] - Sachi to write proposals for PTF 307, 312, and 313.
] - Stu to enter new PTF item for save/restart/reset issue.
] - JimG to write proposals for PTF 517, 533, and 534.
] - Chas to write proposal for PTF 296.
] - Francoise to lookup wording for PTF 524 in VHPI.
] - Francoise will open a new PTF issue to look for
] situations like 25.6.15,
] where multiple methods are used access the same object enclosure
] - Chas to reword proposal for PTF 525.
] - Draft a straw man proposal using a clean slate with no
] concern for
] existing PLI/VPI on the best way to represent all Verilog and
] SystemVerilog kinds and types. This straw man will then
] be used as a
] basis for discussing backward compatibility with the
] existing reg, net,
] variables, functions, and parameter diagrams. It may be
] decided that
] full backward compatibility is not possible, or is not
] the best approach
] moving forward.
] - Sachi will file a PTF item for the clarification of what
] can be done
] at ROsync time and putting values in future times.
] - Francoise to file a PTF item that asks to specify the
] order that iteration
] occur in, when the order is important.
] - Steve to add ETF item for Annex C to remove the
] Informative label, but
] still allow the contents to be option
]
] --
] Charles Dawson
] Senior Engineering Manager
] NC-Verilog Team
] Cadence Design Systems, Inc.
] 270 Billerica Road
] Chelmsford, MA 01824
] (978) 262 - 6273
] chas@cadence.com
]
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Received on Wed Dec 8 08:14:36 2004