Re: [sv-cc] SV-CC Meeting minutes for 01/26/2005

I'm confused. Is there a resolution to the question about the 1-1 transition
from gen scope to gen var? Chas added a new proposal, but that was only a
proposal. I don't see from the minutes a resolution of that proposal.

Shalom

> - Item 313 PTF 296: Generate stmts will need change made in VPI
> - Friendly amendment to memory to reg array and add a vpiMemory label.
> JimV/Francoise. PASSED as amended (unanimous)
> - Does SystemVerilog handle generates?
> We should add gen scope array to the module diagram in systemVerilog
> as well as the interface and program diagrams. We should add gen scope
> to the scope class in systemVerilog. We should open a new item to change
> the systemVerilog stuff.
> Francoise and Chas to investigate what to do for systemVerilog and generates.
> - Chas et all, to look into the 1 to 1 transition from gen scope to gen var
> in 1364. Should it be a 1 to many transition?
> Chas added a new proposal. Done.

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
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