RE: [sv-cc] SV-CC Meeting minutes for 01/26/2005

Chas.,

I have one more editing question, that I missed bringing up during the CC
meeting. The e-mail message below implies that there will be a new Mantis
item created to add generate diagrams to the P1800 LRM. Just looking at the
summary descriptions, I do not see an item for this. What is the status?

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
  

> -----Original Message-----
> From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On
> Behalf Of Jim Vellenga
> Sent: Wednesday, January 26, 2005 12:25 PM
> To: Shalom.Bresticker@freescale.com; Charlie Dawson
> Cc: SV-CC
> Subject: RE: [sv-cc] SV-CC Meeting minutes for 01/26/2005
>
> Yes, Charles, the minutes should probably be amended to
> indicate more precisely what we decided.
>
> Shalom, what happened was that the group voted unanimously to
> approve Charles updated proposal 313-3.[fm|pdf], which leaves
> one single-headed, single-ended arrow coming from a gen scope
> array to the corresponding gen var. This means that each gen
> scope array has only one gen var.
>
> The friendly amendment was to eliminate memory as an object
> (as already approved earlier) and to replace it by an
> iteration on vpiMemory to reg array. Chas has captured the
> friendly amendment in the posted 313-4.[fm|pdf]
>
> Charles or someone will put in a separate Mantis item to add
> the generate diagrams to 1800 as well, and to generalize them
> to include relations to interfaces and programs.
>
> Regards,
> Jim V.
> ---------------------------------------------------------
> James H. Vellenga 978-262-6381
> Engineering Director (FAX) 978-262-6636
> Cadence Design Systems, Inc. vellenga@cadence.com
> 270 Billerica Rd
> Chelmsford, MA 01824-4179
> "We all work with partial information."
> ----------------------------------------------------------
>
>
>
> ] -----Original Message-----
> ] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On
> ] Behalf Of Shalom.Bresticker@freescale.com
> ] Sent: Wednesday, January 26, 2005 3:12 PM
> ] To: Charlie Dawson
> ] Cc: SV-CC
> ] Subject: Re: [sv-cc] SV-CC Meeting minutes for 01/26/2005
> ]
> ] I'm confused. Is there a resolution to the question about the
> ] 1-1 transition
> ] from gen scope to gen var? Chas added a new proposal, but
> ] that was only a
> ] proposal. I don't see from the minutes a resolution of that
> proposal.
> ]
> ] Shalom
> ]
> ]
> ] > - Item 313 PTF 296: Generate stmts will need change made in VPI
> ] > - Friendly amendment to memory to reg array and add a
> ] vpiMemory label.
> ] > JimV/Francoise. PASSED as amended (unanimous)
> ] > - Does SystemVerilog handle generates?
> ] > We should add gen scope array to the module diagram
> ] in systemVerilog
> ] > as well as the interface and program diagrams. We
> ] should add gen scope
> ] > to the scope class in systemVerilog. We should open
> ] a new item to change
> ] > the systemVerilog stuff.
> ] > Francoise and Chas to investigate what to do for
> ] systemVerilog and generates.
> ] > - Chas et all, to look into the 1 to 1 transition from
> ] gen scope to gen var
> ] > in 1364. Should it be a 1 to many transition?
> ] > Chas added a new proposal. Done.
> ]
> ] --
> ] Shalom Bresticker Shalom.Bresticker
> ] @freescale.com
> ] Design & Verification Methodology Tel:
> ] +972 9 9522268
> ] Freescale Semiconductor Israel, Ltd. Fax:
> ] +972 9 9522890
> ] POB 2208, Herzlia 46120, ISRAEL Cell:
> ] +972 50 5441478
> ]
> ] [ ]Freescale Internal Use Only [ ]Freescale Confidential
> ] Proprietary
> ]
> ]
> ]
>
>
>
Received on Wed Feb 2 10:34:48 2005