Section 5.1 contains the statement:
"A
variable can be static (storage allocated on instantiation and never
de-allocated) or automatic (stack storage allocated on entry to a task, function
or named block and de-allocated on exit).”
-
automatic variables can also be allocated in
unnamed blocks so the word "named" should be removed.
Section 5.1 should include genvars in the list of constants supported in Verilog 2001.
Section 5.1 includes the statement "C constants are either literals, macros or enumerations. There is also a const, keyword but it is not enforced in C." It seems like this entire paragraph should be removed, but the second sentence is untrue according to the ANSI C standard and several compiler implementations so at a minimum it should be removed.
The BNF for block_variable_declaration in section 5.2 contains a required "lifetime" component that should be optional.
When multiple variables are declared within a single statement, the BNF in 5.2 requires all variables in the statement to be initialized or none of them. For example, the following appears to be illegal:
int a, b=0;
Is there a reason to not allow
initialized and non-initialized variable declarations together? This is true for block_variable_declaration and for list_of_variable_identifiers_or_assignments.
In section 5.3 there is a brief
discussion about the meaning of a const class object. If a class object is going to be treated as
const then it seems like it should be possible to declare class methods as
"const" otherwise there is no way to determine if a method can be
called for a const class object.
Section 5.4 includes both of the following seemingly contradictory statements:
- "A variable can be declared
with an initializer, which must be a constant
expression."
Section 5.5 contains the statement "If an initializer is used, the keyword static must be specified to make the code clearer." Should this say that either static OR automatic must be specified?
Near the end of section 5.5 there is a restriction that "automatic or dynamic variables cannot be used to trigger an event expression...". This restriction does not exist in Verilog 2001 for automatic variables and it is valid to have forks within an automatic task where one forked process triggers another process based on a local variable.
The BNF in section 5.2 seems to allow variables to have a lifetime of automatic anywhere that a variable can be declared, including at module scope. I didn't see anywhere that explicitly says this is illegal to do except that section 5.5 indicates "data declared inside a module or interface but outside a task, process or function is local in scope and static in lifetime". It would be nice if automatic variables outside of tasks, functions and blocks were explicitly made illegal.