Section 21.2

Change as shown in blue.

ma #(.p1(3), .p2(int)) u1(i,o); //redefines p2 to a type of int

endmodule

SystemVerilog adds the ability for local parameters to be declared in a generate block. Local parameters can also be declared in a package or in a compilation unit scope. In these contexts, the parameter keyword may be used as a synonym for the localparam keyword."

$ can be assigned to parameters of integer types. A parameter to which $ is assigned shall only be used wherever $ can be specified as a literal constant.