System Verilog
LRM Changes to Draft 6
Friday, April 04, 2003
Status Legend: Open, Remove Note, Change, No Change
ID	Committee	Section	Description	Status	Changes
LRM-347	SV-EC	A.8.1	BNF missing Bold on }.	Change	Section A.8.1
LRM-348	SV-AC	A.2.10	Add use of () to property_expr and multi_clock_property_expr. Add conditional on not in property_spec.	Change	Section A.2.10
LRM-349	SV-AC	17.13	Change reference and clarify rules.	Change	Section 17.13
LRM-350	SV-AC	17.13	Change title of table	Change	Section 17.13
LRM-351	SV-AC	17.13	Change reference to table and title of table	Change	Section 17.13
LRM-352	SV-AC	17.13	Change reference to table.	Change	Section 17.13
LRM-353	SV-AC	17.13	Change reference to table.	Change	Section 17.13
LRM-354	SV-AC	17.10	Correct BNF in Syntax block to match change in BNF	Change	Section 17.10
LRM-355	SV-AC	17.11	Correct BNF in Syntax block to match change in BNF	Change	Section 17.11
LRM-356	SV-AC	G	Insert the attached as between Annex F and Annex G as the new Annex G	Change	Section G
LRM-357	SV-EC	8.10	Fix incorrect text	Change	Section 8.10
LRM-358	SV-EC	3.10.2	Fix table entry	Change	Section 3.10.2
LRM-359	SV-CC	Ack	Change spelling of name in acknowledgements	Change	Section Ack
LRM-360	SV-EC	A.1.9 12.4	Missing bold on braces	Change	Section 12.4
					Section A.1.9
LRM-361	SV-CC	26.4.4	Replace handle with chandle in the examples	Change	Section 26.4.4
LRM-362	SV-CC	26.4.5	Replace handle with chandle	Change	Section 26.4.5
LRM-363	SV-CC	10.6 26.4.4 26.6 A.2.6	Add ; at end of import/export declarations.	Change	Section 10.6
					Section 26.4.4
					Section 26.6
					Section A.2.6
LRM-364	SV-CC	D.6.4	Replace handle with chandle	Change	Section D.6.4
LRM-365	SV-CC	D.7.7	Replace handle with chandle	Change	Section D.7.7
LRM-366	SV-CC	D.7.9	Replace handle with chandle	Change	Section D.7.9
LRM-367	SV-CC	E.1	Make a new section to correctly represent the header file	Change	Section E.1
LRM-378	SV-EC	9.8.2	Correct example to use task instead of function	Change	Section 9.8.2