SV-EC
Milestones and Meeting Schedule
24-Mar-03
Meeting Date	Milestone Date	Meeting Objective/Milestone
March 31, 2003		Cancel
	April 1, 2003	Technology Freeze, only clarification and editing - Draft 4 out
April 7, 2003		Review Draft 4
April 14, 2003		Complete Draft 4 review
April 21, 2003		Complete Draft 5 review
	April 25, 2003	Complete vote on sending LRM to board in committee
	May 1, 2003	LRM to Accellera board
	June 1, 2003	System Verilog 3.1 complete
Meetings are from 11am to 1pm PST
The call information for the meetings is:
	(877) 233.7845	US - Toll Free
	(505) 766.5458	International - Caller paid
	516134	Participant code
	Section Progress
	Key: Open -> AI -> Done -> Approved
	Section	Title	Sub-Sections	Status	Scheduled Completion
	1	Introduction to System Verilog	None	-	-
	2	Literal Values	None	-	-
	3	Data Types	4-8, 12, 14	Done	-
	4	Arrays	6-12	Done	-
	5	Data Declarations	7	Done	-
	6	Attributes	None	-	-
	7	Operators and Expressions	5, 10	Done	-
	8	Procedural Statements and Control Flow	7	Done
	9	Processes	6, 7, 9	Done
	10	Tasks and Functions	1, 3.2, 4, 5	Done
	11	Classes	1-24	Done
	12	Inter-Process Synchronization and Communication	1-9	Done
	13	Clocking Domains	1-11	Done
	14	Deleted in Draft 3
	15	Program Block	1-9	Done
	16	Assertions	None	-	-
	17	Hierarchy	None	-	-
	18	Interfaces	None	-	-
	19	Parameters	None	-	-
	20	Random Constraints	1-21	Done
	21	Configuration libraries	None	-	-
	22	System tasks and system functions	None	-	-
	23	Compiler Directives	None	-	-
	24	Features under consideration for removal from System Verilog	None	-	-
	A	Formal Syntax	New BNF	Started
	B	Keywords	Add	Started
	C	String Methods	All	Done
	D	Linked Lists	All	Done
	E	Glossary	None	-	-
	F	Bibliography	None	-	-
	Addition Items	Description	Owner	Status	Scheduled Completion
	EXT-19	Scheduling Semantics	Phil Moorby	Done	CH-112 closes
	EXT-18	Handles	SV-CC	Done	CH-102 closes
	EXT-20	Export/Extern	SV-CC	Done	CH120 closes
	TRN-7	Can packed arrays accept reals	David S.	Done	SV-BC58 closes