
Post 3.1 SystemVerilog Issues

Number	Originator	Committee	Category	Description	Status
Post-1	Surrendra Dudani	SV-AC	New constructs	Expect support (blocking assertions in testbench)	Open
Post-2	Surrendra Dudani	SV-AC	New constructs	Assume construct (use of properties for and constraints with assumptions)	Open
Post-3	Surrendra Dudani	SV-AC	New constructs	Clocked assignment (variable declarations and assignments in clock domain)	Open
Post-4	Surrendra Dudani	SV-AC	New constructs	Complete support for templates (type checking, extend to all SV)	Open
Post-5	Surrendra Dudani	SV-AC	Usability features	Use of attributes in assertions	Open
Post-6	Surrendra Dudani	SV-AC	Usability features	Debug and usability features (access to dynamic variables and sampled values, system controls)	Open
Post-7	Karen Pieper	SV-BC	Refinement	Handling of separate compilation	Open
Post-8	Jonathan Bradford	SV-BC	Clarification	Clarification of the use of "compatible" within the LRM. Section 4.8 Arrays as arguments vs. 4.7 Array assignment vs. 7.14 indicates an inconsistency of equivalence versus assignment compatible.	Open
Post-9	Jonathan Bradford	SV-BC	Clarification	Definition of how all data_types can be passed through module ports and parameters and when ref is required.	Open
Post-10	Dave Rich	SV-BC	Clarification	Clarification of longest static prefix	Open
Post-11	Dave Rich	SV-BC	New constructs	Add support for packing/unpacking cast	Open
Post-12	Dave Rich	SV-BC	Extension	Extend VCD dump format for SV types	Open
Post-13	Joao	SV-CC	Extension	Complete support of VPI for all 3.1 features	Open
Post-14	Jay Lawrence	SV-CC	Clarification	Clarify use of strings with DPI	Open
Post-15	Joao	SV-CC	Clarification	Resolve open versus dynamic array terminology	Open
Post-16	Joao	SV-CC	Extension	Representation of SV data types	Open
Post-17	Arturo Salz	SV-EC	Dynamic Abstract Type Extension	More string manipulation routines (for example Pattern matching using Perl-like matching)	Open
Post-18	Faisal Haque	SV-EC	Dynamic Abstract Type Extension	Pack/Unpack functions for classes	Open
Post-19	Michael Burns/Kevin Cameron	SV-EC	Process control and synchronization Extensions	Provide support for fine grain control of spawned threads.	Open
Post-20	Dave Rich	SV-BC	Process control and synchronization Extensions	Investigate unification of always_comb and always @* implicit event semantics with explicit event control semantics	Open
Post-21	Arturo Salz	SV-EC	Random Constraint Extensions	Stream generation (random support)	Open
Post-22	Arturo Salz	SV-EC	Random Constraint Extensions	Random case statement	Open
Post-23	Arturo Salz	SV-EC	Testbench Extenions	Support for namespaces for (combining files into a testbench or verification IP)	Open
Post-24	Arturo Salz	SV-EC	Testbench Extenions	Functional coverage goal specification	Open
Post-25	Arturo Salz	SV-EC	Testbench Extenions	Reacting to assertions	Open
Post-26	Neil Korpusik	SV-EC	Basic Language Features	Add support for "virtual interfaces/ports" (store or pass by reference "bundles of wires")	Open
Post-27	Arturo Salz	SV-EC	Basic Language Features	$system and other system tasks on new data types	Open
Post-28	Peter Flake	SV-EC	Basic Language Features	Support for optional order of lifetime, data-type, and signing to support syntactical consistency with C and backward compatibility with Verilog-2001.	Open
Post-29	Peter Flake	SV-EC	Basic Language Features	Support type as part of $bits (just like sizeof in C)	Open
Post-30	Michael Burns	SV-EC	Extension	Synthesizable testbench components.	Open
Post-31	Adrzej Litwiniuk	SV-CC	Clarification	Resolve contradiction between Table 11-1 and 26.4.1.4 wrt garbage collection from C handle	Open