Section 13.1 - Scheduling issues (Stuart/Cadence) [Basic, System]
- interfaces allow non-deterministic behavior due to scheduling order
- need ability to control scheduling order

Interfaces provide plenty of opportunities for users to create non-deterministic designs (i.e. designs whose behavior is dependent on the scheduling order that a particular simulator happens to use.)

What are the rules and the capabilities that System Verilog will provide to enable users to create interfaces that do NOT result in non-deterministic designs?

For example: Can the user model the equivalent of non-blocking delays & delta cycles within interfaces?
Can the user do the equivalent of signal resolution for multiple processes that simultaneously update the state of an interface?