Replace in Section 3.1:

“System Verilog 3.1 adds string and class data types, and”

with

“System Verilog 3.1 adds string, handle, and class data types, and”

Insert the following new section in Chapter 3.

Section 3.7 Handle data type

The handle data type represents storage for pointers passed across the DirectC interface. The size of this type is platform dependent and must be at least large enough to hold a pointer on the machine in which the simulator is running. The syntax to declare a handle is as follows:

handle variable_name;

where variable_name is a valid identifier. Handles will always be initialized to the value null, which has a value of 0 on the C side, which represents a non-existent handle. Handles are very restricted on their usage, with the only legal uses being as

follows:

- only the following operators are valid on handle variables:

· equality (==), inequality (!=) with another handle or with null

· case equality (===), case inequality with another handle or with null (same semantics as == and !=)

- only the following assigments can be made to a handle

· assignment from another handle

· assigment to null

- handles can be inserted into associative arrays (ref section 4.9), but no guarantees will be made on relative ordering of any two entries in such an associative array, even between successive runs of the same simulation.

- handles can be used within a class

- handles may be passed as arguments to functions or tasks

- handles can be returned from functions

The use of handles are restricted as follows:

- ports may not have the handle data type

- handles may not be assigned to variables of any other type

- handles cannot be used:

· in any expression other than as permited above

· as a ports

· in sensitivity lists or event expressions

· in continuous assigments

· in structures or unions

· in packed arrays