Remove editor’s note before this section.
Remove editor’s notes:
Editor’s Note: Is
the “DirectC” .name to be used in SystemVerilog?
Editor’s Note: I
took the liberty of adding “handle” to the keyword list in Annex B
Editor’s Note: Is
“null” also a SystemVerilog keyword?.
Remove editor’s note:
Editor’s Note:
BC-5 and BC8-8 modified the same sentence. I merged the two changes together.
Remove editor’s note:
Editor’s Note: I
took the liberty of adding “alias” to the keyword list in annex B, under this
change number.
Remove editor’s note:
Editor’s Note: BC19-1 said to add ^~ to lines
2 and 11. I made the second change to line 10 was instead of 11.
Change the first two sentences as shown in red:
Procedural
statements are introduced by the
following:
initial // enable this statement at the beginning of
simulation and execute it only once
Remove editor’s notes:
Editor’s Note: The
deleted sentence should be kept. The new wording is too informal for a
technical language reference manual.
Editor’s Note: The
added comment is not correct. Statements within an initial procedure do not
necessarily execute at the beginning of simulation, as there can be time and/or
event controls before the statement
Editor’s Note: I
took the liberty of adding “final” to the list of keywords in Annex B.
Remove editor’s note:
Editor’s Note:
Subheading titles were added for clarity, due to additional text on for loops.
Remove editor’s note:
Editor’s Note: I
took the liberty of replacing “similar routines” with the actual PLI routine
name.
Remove editor’s note:
Editor’s Note: The
process statement is deprecated, in favor of fork...join none
(see below).
Remove editor’s note:
Editor’s Note: I
implemented change EC-CH89 for the preceding two paragraphs slightly
differently than specified to make the wording flow better.
Remove editor’s note:
Editor’s Note:
EC-CH100 did not include the changes to the preceding paragraph. I added those
because they seemed appropriate..
Remove editor’s note:
Editor’s Note: The
subsection title was added by the editor, both for clarity and to give balance
with the addition of subsection 10.3.2 that was added.for
draft 1.
Make changes shown in red:
SystemVerilog allows using
the void data type to
discard a function’s return value and is done by
casting the function to the void type, or by assigning the
function return to the void type:
Remove editor’s notes:
Editor’s Note:
This entire section is new for draft 1. Only the Section titles have been
highlighted as new text.
Editor’s Note: The
material inserted here is as it was provided by the SV-EC committee. The editor
feels it is written in a tutorial style, and needs considerable rewording to be
appropriate for the SystemVerilog LRM. See section 11.4 as one example where
re-wording may be needed.
Remove editor’s notes:
Editor’s Note: The
Editor vehemently objects to reserving the keywords new, this and
super! (see Annex B)
Editor’s Note: Is
the “DirectC” .name to be used in SystemVerilog?
Change the function declaration in the last example as shown in red:
function integer
test;
Remove editor’s note:
Editor’s Note:
Verilog syntax is “function integer”. Is the “integer function” above correct?
Remove editor’s notes:
Editor’s Note:
This entire section is new for draft 1. Only the Section titles have been
highlighted as new text.
Editor’s Note: Are
semaphore and mailbox really “primitives” in the Verilog HDL and PLI sense of
“primitive”?
Remove editor’s note:
Editor’s Note: Is
the preceding paragraph supposed to be a part of the try_peek()
subsection? It seems like it belongs at the end of 19.4, before any of the
subsections.
Remove editor’s note:
Editor’s Note:
This entire section is new for draft 1. Only the Section titles have been
highlighted as new text.
Remove editor’s note:
Editor’s Note: The
remaining subsections in.this section were originally
in section 14 of 3.1 draft 2
Remove editor’s note:
Editor’s Note: The
“primitive” is a keyword with unique meaning in Verilog. It shouldn’t be used
in the line above
Remove editor’s note:
Editor’s Note:
“one fell swoop” may not be appropriate for an international standard.
Remove editor’s note:
Editor’s Note:
Other than the intro, this entire section was moved to the end of section 13.
Remove editor’s note:
Editor’s Note:
This entire section is new for draft 1. Only the section titles have been
highlighted as new text.
Remove the following paragraph:
Note: While this
does not represent a conflict with SystemVerilog 3.0, it may require a special
pre-initial pass at run-time, which may need changes to the initial
SystemVerilog simulation cycle. This is one of the requirements that
differentiates a program from a module.
Remove editor’s note:
Editor’s Note: The
preceding paragraph seems rather odd for a standard. Is it necessary to state
this at all?
Remove editor’s note:
Editor’s Note: This
entire section is superceded by the following section (added for SV 3.1 draft
3).
Remove editor’s note:
Editor’s Note:
This entire section is new for draft 3, and replaces the SV 3.0 section on
assertions. Only the Section titles have been highlighted as new text.
Remove editor’s note:
Editor’s Note:
This entire section is new for draft 2. Only the Section titles have been
highlighted as new text.
Make changes shown in red:
class MyYXPair extends
XYPair
function void pre_randomize();
super.pre_randomize();
$display("Before randomize x=%0d,
y=%0d", x, y);
endfunction
function void post_randomize();
super.post_randomize();
$display("After randomize x=%0d,
y=%0d", x, y);
endfunction
endclass
Remove editor’s note:
Editor’s Note:
“function” is paired with “endtask”. Are these tasks
or functions?.
Remove editor’s note:
Editor’s Note: I
took the liberty of changing the final “begin” to “end”
Remove editor’s note:
Editor’s Note: I
took the liberty of changing the final “endtask” to “endfunction”
Remove editor’s note:
Editor’s Note:
This entire section is new for draft 1. Only the Section titles have been
highlighted as new text.
Remove editor’s note:
Editor’s Note: Is
it being suggested that SystemVerilog tools build in these methods? If
so, something to that effect should be stated in this intro.