Section 12.3

Change Section 12.3 to 12.2.4.

Section 13.2

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The clocking_event designates a particular event to act as the clock for the clocking domain. Typically, this expression is either the posedge or negedge of a clocking signal. The timing of all the other signals specified in a given clocking domain are governed by the clocking event. All input or inout signals specified in the clocking domain are sampled when the corresponding clock event occurs. Likewise, all output or inout signals in the clocking domain are driven when the corresponding clock event occurs. Bidirectional signals (inout) are sampled as well as driven.

Section 13.7

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In this example, a simple test module includes two clocking domains. The program construct used in this example is discussed in section 15. In this example, it can be considered a module.

Section 13.8

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A clocking encapsulates a set of signals that share a common clock, therefore, specifying a clocking domain using a SystemVerilog interface can significantly reduce the amount of code needed to connect the testbench. Furthermore, since the signal directions in the clocking domain within the test-bench are with respect to the test-bench, and not the design under test, a modport declaration can appropriately describe either direction. A test-bench can be contained within a program module, and its ports can be interfaces that correspond to the signals declared in each clocking domain. The interface’s wires will have the same direction as specified in the clocking domain when viewed from the test-bench side (i.e., modport test), and reversed when viewed from the device under test (i.e., modport dut).

Section 13.10

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What constitutes a cycle is determined by the default clocking in effect (see section 13.11). If no default clocking has been specified for the current module, interface, or program then the compiler will issue an error.

Section 13.11

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Only one default clocking can be specified in a program, module, or interface. Specifying a default clocking more than once in the same program or module shall result in a compiler error.

Section 13.14

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The event_count is an integral expression that optionally specifies the number of clocking events (i.e. cycles) that must pass before the statement executes. Specifying a non-zero event_count blocks the current process until the specified number of clocking events have elapsed, otherwise the statement executes at the current time. The event_count uses a syntax similar to the cycle-delay operator (see section 13.10), however, the synchronous drive uses the clocking domain of the signal being driven and not the default clocking.