The ## operator can be used to delay execution by a specified number of clocking events, or clock cycles.
The syntax for the cycle delay statement is:
## [ expression ];
The expression can be any SystemVerilog expression that evaluates to a positive integer value.
What represents a cycle is determined by the default clocking in effect (see Section 12.9.1). If no default clocking has been specified for the current module, interface, or program then the compiler will issue an error.
Example:
## [5]; //
wait 5 cycles using
## [j
+ 1]; // wait j+1 cycles using
the default clocking
One clocking can be specified as the default for all cycle delay operations within a given module, interface, or program.
The syntax for the default cycle specification statement is:
default clocking_decl ; // clocking declaration
or
default clocking clocking_name ; // existing clocking
The clocking_name must be the name of a clocking domain.
Only one default clocking can be specified in a program, module, or interface. Specifying a default clocking more than once in the same program or module will result in a compiler error.
A default clocking specified in a module is only valid in that particular module and not in any of its sub-modules.
Example 1. Declaring a clocking as the default:
program test( input bit clk, input reg [15:0] data )
default
clocking bus @(posedge clk);
inout data;
endclocking
## 5;
if( bus.data == 10 )
## 1;
else
...
endprogram
Example 2. Assigning an existing clocking to be the default:
clocking busA @(posedge clk1); ... endclocking
clocking busB @(negedge clk2); ... endclocking
module cpu( interface
y )
default
clocking busA ;
initial begin
## 5; //
use busA => (posedge
clk1)
...
end
endprogram