Section 8.1 Starting at first paragraph make the following changes in blue.

One introduces procedural statements by the following:

initial // do this statement once at the beginning of simulation

final // do this statement once at the end of simulation

always, always_comb, always_latch, always_ff // loop forever (see section 9 on processes)

task // do these statements whenever the task is called

function // do these statements whenever the function is called and return a value

SystemVerilog has the following types of control flow within a process

— Selection, loops and jumps

— Task and function calls

— Sequential and parallel blocks

— Timing control

—

Verilog procedural statements are in initial or always blocks, tasks or functions. SystemVerilog adds a final block that executes at the end of simulation.

Insert the following between Section 8.5 and Section 8.6 with this becoming the new Section 8.6 and succeeding paragraphs being renumbered.

8.6 Final Blocks

The final block is like an initial block, defining a procedural block of statements, except that it occurs at the end of simulation time and executes without delays. A final block is typically used to display statistical information about the simulation.

final_construct ::= final function_statement

The only statements allowed inside a final block are those permitted inside a function declaration. This guarantees that they execute within a single simulation cycle.

After one of the following conditions occur, all spawned processes are terminated, all pending PLI callbacks are canceled, and then the final block executes.

- The event queue is empty

- Execution of $finish

- Termination of all program blocks, which executes an implicit $finish

- PLI execution of tf_dofinish or similar routines.

final

begin

$display(“Number of cycles executed %d”,$time/period);

$display(“Final PC = %h”,PC);

end

Execution of $finish or tf_dofinish from within a final block will cause the simulation to end immediately. Final blocks can only trigger once in a simulation.

Final blocks execute before any PLI callbacks that indicate the end of simulation.

Add the following paragraph after the last paragraph in Section 9.1

Final blocks execute in an arbitrary but deterministic sequential order. This is possible because final blocks are limited to the legal set of statements allowed for functions. SystemVerilog does not specify the ordering, but implementation should define rules that will preserve the ordering between runs. This helps keep the output logfile stable since final blocks are mainly used for displaying statistics.