Change last paragraph in Section 13.3 as follows (blue for additions, strike-through for deletions).

From:

An input skew of #0 forces a skew of zero. Input signals with zero skew are sampled at the same time as their corresponding clock edge, but to avoid races the sampling is done after all nonblocking assignments (NBA) have been processed (see Section 15.7). Likewise, output signals with zero output skew are driven at the same time as their specified clock edge, but immediately before read-only synchronize time (before advancing time). A detailed explanation for this event ordering is covered in Section 15.7.

To:

An input skew of #0 forces a skew of zero. Inputs with zero skew are sampled at the same time as their corresponding clocking event, but, to avoid races, they are sampled at the start of the verification phase (after processing non-blocking assignments). Likewise, outputs with zero skew are driven at the same time as their specified clocking event, but at the end of the verification phase. A detailed explanation for this event ordering is covered in Section 15.7.