In Section 14.4.1 rename section to Drives and non-blocking assignments

In Section 14.4.1 replace first paragraph (following):

All zero-delay signal drives (no cycle delay and no skew) are queued and propagated in one fell swoop, right before read-only synchronize time. Zero-delay signal drives resemble Verilog nonblocking assignments, thus, reading the value of an inout signal immediately after it has been driven will yield the previous (sampled) value, not the driven value:

if( bus.data == 31 )

bus.data <= 27;

y = bus.data; // y is 31 (not 27)

It is illegal to drive a clocking domain signal with zero delay using = (blocking drive). If the drive specifies a delay or an output skew then the blocking drive is allowed.

with:

Synchronous signal drives are queued and processed at the end of the verification phase, like non-blocking assignments, that is, they are propagated in one fell swoop without process execution in between drives.

A key feature of inout clocking domain variables and synchronous drives is that a driven signal value does not change the clock domain input. This is because reading the input always yields the last sampled value, and not the current signal value. In this respect, an inout clocking domain variable resembles non-blocking assignments since reading the variable immediately after it has been assigned will yield the previous value, not the assigned value.

// bus.data is a clock domain inout, y is a variable

if( bus.data == 5 ) if( y == 5 )

bus.data = 0; y <= 0;

$display( bus.data ); $display( y ); // both display 5