Rev 5, Phil Moorby, 19-Dec-02
In order
to mix verification and design code together, which implies combining
clock-cycle and event-based simulation semantics, we
must precisely define the order and flow of the simulation processing performed
during each time slot. The Verilog standard LRM has defined the order of same
time scheduling queues for design events, and this needs to be expanded and
clarified along with the various types of PLI callbacks and what actions are
allowed to occur during these callbacks.
All
processing at a particular simulation time slot is divided into 4 ordered
phases: design, clocking, verification, and read-only. The phases are strictly ordered, meaning that
there is no going back to a previous phase in the same time slot.
Design phase |
Clocking phase |
Verification phase |
Read-only phase |
|
Start: PLI
callbacks. Execute
code. Do value
changes. goto
Start; #0
events. goto
Start; PLI
callbacks. goto
Start; NBA updates. PLI
callbacks. goto
Start; |
PLI callbacks(1). Detect
clocks. Sample
design variables. Evaluate
next state of properties. Detect
design errors. Do
coverage analysis. |
Mirror
of design phase events with same loop back semantics. |
PLI callbacks(2). |
(1) PLI
code is not allowed to create design phase events at current time.
(2) PLI
code is not allowed to create any events (current definition of rosync).
The design
phase includes the usual design procedural code executions, design variable
value change events, and the design NBA update events. This phase continues to
loop on itself until there are no more design events before moving onto the
next phase.
The
clocking phase occurs if a clock in any clocking domain is triggered. This
phase includes detection of which clocks have occurred, samples the appropriate
design variables, and processes all properties to determine their next state.
Other operations are to detect design errors and do the coverage analysis.
There are no loop backs within this phase.
The verification
phase executes verification program code. All events scheduled to occur in the
current time slot are processed in a manner similar to the design phase event
loops. In this phase, it is an error if any clocking domain clocks are
triggered at the current time slot, either directly or by zero-delay signal
propagations. It is also an error in
this phase to drive a sampled design variable with an immediate blocking
assignment.
The
read-only phase is not allowed to further create value changes on any kind of
variable, and there will therefore be no reason to loop back to previous phases
at the current time slot.
The
sampling of design variables during the clocking phase is either immediate or
delayed, depending on the clock domain specification. Delayed sampling of design variables always
takes the value of the variable at the read-only phase of the appropriate time
slot.
A special
delay of 1step is defined to enable the ability to sample design variables
effectively at the current time but before any variable has changed value. The 1step delay is defined to be the smallest
possible delay throughout the design and verification code, and simulation
ticks are defined as being 1step apart.
A 1step delay is allowed to be passed in as a parameter similarly to
other parameters of type time.
It is
possible to call a design task from verification code. The task starts
executing immediately in the current verification phase, and any zero-delay suspensions
of the control thread continues in the same verification phase. If the task suspends for a non-zero delay,
then the code resumes execution in the design phase of that future time slot. When control finally returns from a delayed design task back to the
verification code, control switches and resumes in the verification phase.